Browse Source

update constraint file to new design

T. Meissner 5 years ago
parent
commit
e64b387455
1 changed files with 18 additions and 7 deletions
  1. 18
    7
      raspiFpga/syn/constraints/RaspiFpga.lpf

+ 18
- 7
raspiFpga/syn/constraints/RaspiFpga.lpf View File

@@ -1,7 +1,18 @@
1
-BLOCK RESETPATHS ;
2
-BLOCK ASYNCPATHS ;
3
-LOCATE COMP "RaspiIrq_o" SITE "11" ;
4
-IOBUF PORT "RaspiIrq_o" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
5
-IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
6
-LOCATE COMP "SpiSte_i" SITE "69" ;
7
-FREQUENCY NET "s_sys_clk" 26.600000 MHz ;
1
+BLOCK RESETPATHS;
2
+BLOCK ASYNCPATHS;
3
+
4
+BANK 0 VCCIO 3.3 V;
5
+BANK 2 VCCIO 3.3 V;
6
+BANK 1 VCCIO 3.3 V;
7
+BANK 3 VCCIO 3.3 V;
8
+
9
+IOBUF ALLPORTS IO_TYPE=LVCMOS33;
10
+
11
+LOCATE COMP "RaspiIrq_o" SITE "11";
12
+LOCATE COMP "SpiSte_i" 	 SITE "3";
13
+
14
+IOBUF PORT "RaspiIrq_o" IO_TYPE=LVCMOS33 PULLMODE=NONE;
15
+
16
+FREQUENCY NET "s_sys_clk" 26.600000 MHz;
17
+
18
+SYSCONFIG SDM_PORT=PROGRAMN  I2C_PORT=DISABLE  SLAVE_SPI_PORT=ENABLE MCCLK_FREQ=26.6;