update constraint file to new design

raspiFpga/syn/constraints/RaspiFpga.lpf

@@ -1,7 +1,18 @@
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-LOCATE COMP "RaspiIrq_o" SITE "11" ;
-IOBUF PORT "RaspiIrq_o" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
-IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
-LOCATE COMP "SpiSte_i" SITE "69" ;
-FREQUENCY NET "s_sys_clk" 26.600000 MHz ;
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+
+BANK 0 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+BANK 1 VCCIO 3.3 V;
+BANK 3 VCCIO 3.3 V;
+
+IOBUF ALLPORTS IO_TYPE=LVCMOS33;
+
+LOCATE COMP "RaspiIrq_o" SITE "11";
+LOCATE COMP "SpiSte_i" 	 SITE "3";
+
+IOBUF PORT "RaspiIrq_o" IO_TYPE=LVCMOS33 PULLMODE=NONE;
+
+FREQUENCY NET "s_sys_clk" 26.600000 MHz;
+
+SYSCONFIG SDM_PORT=PROGRAMN  I2C_PORT=DISABLE  SLAVE_SPI_PORT=ENABLE MCCLK_FREQ=26.6;