library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity FiRoCtrlE is
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generic (
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EXTRACT : boolean := true
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);
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port (
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--+ system if
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Clk_i : in std_logic;
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Reset_i : in std_logic;
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--+ ctrl/status
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Start_i : in std_logic;
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Wait_i : in std_logic_vector(7 downto 0);
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Run_i : in std_logic_vector(7 downto 0);
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--+ rnd data
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DataValid_o : out std_logic;
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Data_o : out std_logic_vector(7 downto 0);
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-- firo
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Run_o : out std_logic;
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Data_i : in std_logic
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);
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end entity FiRoCtrlE;
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architecture rtl of FiRoCtrlE is
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signal s_firo_run : std_logic;
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signal s_firo_valid : std_logic;
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type t_neumann_state is (BIT1, BIT2, BIT3, BIT4);
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signal s_neumann_state : t_neumann_state;
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signal s_neumann_buffer : std_logic_vector(2 downto 0);
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type t_register_state is (SLEEP, COLLECT);
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signal s_register_state : t_register_state;
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signal s_register_enable : std_logic;
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signal s_register_din : std_logic_vector(1 downto 0);
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signal s_register_data : std_logic_vector(8 downto 0);
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signal s_register_counter : unsigned(2 downto 0);
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signal s_register_length : natural range 1 to 2;
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signal s_data : std_logic_vector(3 downto 0);
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begin
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Run_o <= s_run when s_register_state = COLLECT else '0';
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s_data <= s_neumann_buffer & Data_i;
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ControllerP : process (Clk_i) is
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variable v_wait_cnt : unsigned(7 downto 0);
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variable v_run_cnt : unsigned(7 downto 0);
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begin
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if (rising_edge(Clk_i)) then
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if (s_register_state = SLEEP) then
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v_wait_cnt := unsigned(Wait_i);
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v_run_cnt := unsigned(Run_i);
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s_firo_run <= '0';
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s_firo_valid <= '0';
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else
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s_firo_valid <= '0';
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if (v_wait_cnt = 0) then
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s_firo_run <= '1';
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else
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v_wait_cnt := v_wait_cnt - 1;
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end if;
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if (v_run_cnt = 0) then
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s_firo_run <= '0';
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elsif (v_run_cnt = 1) then
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s_firo_valid <= '1';
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else
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if (v_wait_cnt = 0) then
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v_run_cnt := v_run_cnt - 1;
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end if;
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end if;
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end if;
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end if;
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end process ControllerP;
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extractor : if EXTRACT generate
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VonNeumannP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Reset_i = '0') then
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s_neumann_state <= BIT1;
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else
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case s_neumann_state is
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when BIT1 =>
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s_register_enable <= '0';
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if (s_firo_valid = '1') then
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s_neumann_buffer(2) <= Data_i;
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s_neumann_state <= BIT2;
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end if;
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when BIT2 =>
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if (s_firo_valid = '1') then
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s_neumann_buffer(1) <= Data_i;
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s_neumann_state <= BIT3;
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end if;
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when BIT3 =>
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if (s_firo_valid = '1') then
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s_neumann_buffer(0) <= Data_i;
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s_neumann_state <= BIT4;
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end if;
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when BIT4 =>
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if (s_firo_valid = '1') then
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s_register_enable <= '1';
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s_register_length <= 1;
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s_register_din <= "00";
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s_neumann_state <= BIT1;
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case (s_data) is
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when x"5" =>
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s_register_din <= "01";
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when x"1" | x"6" | x"7" =>
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s_register_length <= 2;
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when x"2" | x"9" | x"b" =>
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s_register_din <= "01";
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s_register_length <= 2;
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when x"4" | x"a" | x"d" =>
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s_register_din <= "10";
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s_register_length <= 2;
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when x"8" | x"c" | x"e" =>
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s_register_din <= "11";
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s_register_length <= 2;
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when x"0" | x"f" =>
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s_register_enable <= '0';
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when others => -- incl. x"3"
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null;
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end case;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process VonNeumannP;
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end generate;
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no_extractor : if not(EXTRACT) generate
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s_register_enable <= s_firo_valid;
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s_register_din(0) <= Data_i;
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s_register_length <= 1;
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end generate;
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Data_o <= s_register_data(7 downto 0);
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ShiftRegisterP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Reset_i = '0') then
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s_register_counter <= (others => '1');
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s_register_state <= SLEEP;
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DataValid_o <= '0';
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else
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case s_register_state is
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when SLEEP =>
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DataValid_o <= '0';
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if (Start_i = '1' and Run_i /= x"00") then
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s_register_state <= COLLECT;
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s_register_data(0) <= s_register_data(8);
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end if;
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when COLLECT =>
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if (s_register_enable = '1') then
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if (s_register_counter = 0) then
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s_register_data <= s_register_din(1) & s_register_data(6 downto 0) & s_register_din(0);
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DataValid_o <= '1';
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s_register_state <= SLEEP;
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elsif (s_register_counter = 1) then
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if (s_register_length = 1) then
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s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
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end if;
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if (s_register_length = 2) then
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s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
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DataValid_o <= '1';
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s_register_state <= SLEEP;
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end if;
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else
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if (s_register_length = 1) then
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s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
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else
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s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
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end if;
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end if;
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s_register_counter <= s_register_counter - s_register_length;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process ShiftRegisterP;
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end architecture rtl;
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