library ieee;
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use ieee.std_logic_1164.all;
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entity RaspiFpgaCtrlE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ System if
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Rst_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalAck_i : in std_logic;
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LocalError_i : in std_logic;
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--+ EFB if
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EfbSpiIrq_i : in std_logic
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);
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end entity RaspiFpgaCtrlE;
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architecture rtl of RaspiFpgaCtrlE is
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--+ EFB SPI slave register addresses
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constant C_SPICR0 : std_logic_vector(7 downto 0) := x"54"; --* ctrl reg 0
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constant C_SPICR1 : std_logic_vector(7 downto 0) := x"55"; --* ctrl reg 1
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constant C_SPICR2 : std_logic_vector(7 downto 0) := x"56"; --* ctrl reg 2
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constant C_SPIBR : std_logic_vector(7 downto 0) := x"57"; --* clk pre-scale
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constant C_SPICSR : std_logic_vector(7 downto 0) := x"58"; --* master chip select
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constant C_SPITXDR : std_logic_vector(7 downto 0) := x"59"; --* transmit data
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constant C_SPIISR : std_logic_vector(7 downto 0) := x"5A"; --* status
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constant C_SPIRXDR : std_logic_vector(7 downto 0) := x"5B"; --* receive data
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constant C_SPIIRQ : std_logic_vector(7 downto 0) := x"5C"; --* interrupt request
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constant C_SPIIRQEN : std_logic_vector(7 downto 0) := x"5D"; --* interrupt request enable
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--+ init fsm types and signals
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type t_init_fsm is (IDLE, SET, ACK, INIT_DONE);
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signal s_init_fsm : t_init_fsm;
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signal s_init_done : boolean;
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signal s_init_wen : std_logic;
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signal s_init_adress : std_logic_vector(G_ADR_WIDTH-1 downto 0);
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signal s_init_data : std_logic_vector(G_DATA_WIDTH-1 downto 0);
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signal s_ctl_wen : std_logic;
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signal s_ctl_adress : std_logic_vector(G_ADR_WIDTH-1 downto 0);
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signal s_ctl_data : std_logic_vector(G_DATA_WIDTH-1 downto 0);
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type t_adress_array is array (natural range <>) of std_logic_vector(G_ADR_WIDTH-1 downto 0);
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constant C_INIT_ADR : t_adress_array := (C_SPICR1, C_SPICR2, C_SPIIRQEN);
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type t_data_array is array (natural range <>) of std_logic_vector(G_DATA_WIDTH-1 downto 0);
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constant C_INIT_DATA : t_data_array := (x"80", x"00", x"18");
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signal s_init_cnt : natural range 0 to C_INIT_ADR'length-1;
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begin
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LocalWen_o <= s_init_wen when not(s_init_done) else s_ctl_wen;
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LocalAdress_o <= s_init_adress when not(s_init_done) else s_ctl_adress;
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LocalData_o <= s_init_data when not(s_init_done) else s_ctl_data;
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InitP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Rst_n_i = '0') then
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s_init_cnt <= 0;
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s_init_fsm <= IDLE;
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else
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FsmC : case s_init_fsm is
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when IDLE =>
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s_init_cnt <= 0;
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s_init_fsm <= SET;
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when SET =>
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s_init_fsm <= ACK;
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when ACK =>
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if (LocalAck_i = '1') then
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if (s_init_cnt = C_INIT_ADR'length-1) then
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s_init_fsm <= INIT_DONE;
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else
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s_init_cnt <= s_init_cnt + 1;
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s_init_fsm <= SET;
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end if;
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end if;
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when INIT_DONE =>
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null;
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when others =>
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null;
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end case FsmC;
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end if;
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end if;
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end process InitP;
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s_init_wen <= '1' when s_init_fsm = SET else '0';
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s_init_adress <= C_INIT_ADR(s_init_cnt);
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s_init_data <= C_INIT_DATA(s_init_cnt);
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s_init_done <= true when s_init_fsm = INIT_DONE else false;
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end architecture rtl;
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