Various projects using Raspberry Pi

FiRoE.vhd 1.9KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library machxo2;
  5. use machxo2.components.all;
  6. entity FiRoE is
  7. generic (
  8. IMP : string := "HDL",
  9. TOGGLE : boolean := true
  10. );
  11. port (
  12. FiRo_o : out std_logic;
  13. Run_i : in std_logic
  14. );
  15. end entity FiRoE;
  16. architecture rtl of FiRoE is
  17. --+ signal for inverter loop
  18. signal s_ring : std_logic_vector(15 downto 0);
  19. signal s_tff : std_logic;
  20. --+ attributes for synthesis tool to preserve inverter loop
  21. attribute syn_keep : boolean;
  22. attribute syn_hier : string;
  23. attribute syn_hier of rtl : architecture is "hard";
  24. attribute syn_keep of s_ring : signal is true;
  25. attribute syn_keep of s_tff : signal is true;
  26. --+ Attributes for lattice map tool to not merging inverter loop
  27. attribute nomerge : boolean;
  28. attribute nomerge of s_ring : signal is true;
  29. begin
  30. FiroRingG : for index in 0 to 30 generate
  31. HdlG : if IMP = "HDL" generate
  32. s_ring(index) <= not(s_ring(index - 1));
  33. end generate HdlG;
  34. LutG : if IMP = "LUT" generate
  35. lut : LUT4
  36. generic map (
  37. init => x"FFFF"
  38. )
  39. port map (
  40. Z => s_ring(i-1),
  41. A => s_ring(i),
  42. B => '0',
  43. C => '0',
  44. D => '0'
  45. );
  46. end generate LutG;
  47. end generate FiroRingG;
  48. s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;
  49. WithToggleG : if TOGGLE generate
  50. tffP : process(Run_i, s_ring(15)) is
  51. begin
  52. if(Run_i = '0') then
  53. s_tff <= '0';
  54. elsif(rising_edge(s_ring(15))) then
  55. s_tff <= not s_tff;
  56. end if;
  57. end process tffP;
  58. FiRo_o <= s_ring(15) xor s_tff;
  59. end generate WithToggleG;
  60. WithoutToggleG : if not(TOGGLE) generate
  61. FiRo_o <= s_ring(15);
  62. end generate WithoutToggleG;
  63. end architecture rtl;