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98 lines
1.9 KiB
98 lines
1.9 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library machxo2;
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use machxo2.components.all;
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entity FiRoE is
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generic (
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IMP : string := "HDL",
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TOGGLE : boolean := true
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);
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port (
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FiRo_o : out std_logic;
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Run_i : in std_logic
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);
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end entity FiRoE;
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architecture rtl of FiRoE is
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--+ signal for inverter loop
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signal s_ring : std_logic_vector(15 downto 0);
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signal s_tff : std_logic;
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--+ attributes for synthesis tool to preserve inverter loop
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attribute syn_keep : boolean;
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attribute syn_hier : string;
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attribute syn_hier of rtl : architecture is "hard";
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attribute syn_keep of s_ring : signal is true;
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attribute syn_keep of s_tff : signal is true;
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--+ Attributes for lattice map tool to not merging inverter loop
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attribute nomerge : boolean;
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attribute nomerge of s_ring : signal is true;
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begin
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FiroRingG : for index in 0 to 30 generate
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HdlG : if IMP = "HDL" generate
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s_ring(index) <= not(s_ring(index - 1));
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end generate HdlG;
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LutG : if IMP = "LUT" generate
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lut : LUT4
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generic map (
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init => x"FFFF"
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)
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port map (
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Z => s_ring(i-1),
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A => s_ring(i),
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B => '0',
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C => '0',
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D => '0'
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);
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end generate LutG;
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end generate FiroRingG;
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s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;
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WithToggleG : if TOGGLE generate
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tffP : process(Run_i, s_ring(15)) is
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begin
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if(Run_i = '0') then
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s_tff <= '0';
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elsif(rising_edge(s_ring(15))) then
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s_tff <= not s_tff;
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end if;
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end process tffP;
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FiRo_o <= s_ring(15) xor s_tff;
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end generate WithToggleG;
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WithoutToggleG : if not(TOGGLE) generate
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FiRo_o <= s_ring(15);
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end generate WithoutToggleG;
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end architecture rtl;
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