library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library machxo2;
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use machxo2.components.all;
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entity RaspiFpgaE is
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port (
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--+ SPI slave if
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SpiSclk_i : inout std_logic;
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SpiSte_i : in std_logic;
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SpiMosi_i : inout std_logic;
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SpiMiso_o : inout std_logic;
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--* interrupt line to raspi
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RaspiIrq_o : out std_logic
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);
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end entity RaspiFpgaE;
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architecture rtl of RaspiFpgaE is
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--+ Wishbone master component
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component WishBoneMasterE is
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generic (
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G_ADR_WIDTH : positive := 8; --* address bus width
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G_DATA_WIDTH : positive := 8 --* data bus width
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
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WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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--+ wishbone inputs
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WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
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LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end component WishBoneMasterE;
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component RaspiFpgaCtrlE is
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port (
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--+ System if
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Rst_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(7 downto 0);
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LocalData_i : in std_logic_vector(7 downto 0);
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LocalData_o : out std_logic_vector(7 downto 0);
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LocalAck_i : in std_logic;
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LocalError_i : in std_logic;
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--+ EFB if
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EfbSpiIrq_i : in std_logic;
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--+ RNG if
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RngStart_o : out std_logic;
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RngWait_o : out std_logic_vector(7 downto 0);
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RngRun_o : out std_logic_vector(7 downto 0);
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RngDataValid_i : in std_logic;
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RngData_i : in std_logic_vector(7 downto 0)
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);
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end component RaspiFpgaCtrlE;
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component FiRoCtrlE is
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generic (
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EXTRACT : boolean := true
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);
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port (
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--+ system if
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Clk_i : in std_logic;
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Reset_i : in std_logic;
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--+ ctrl/status
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Start_i : in std_logic;
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Wait_i : in std_logic_vector(7 downto 0);
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Run_i : in std_logic_vector(7 downto 0);
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--+ rnd data
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DataValid_o : out std_logic;
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Data_o : out std_logic_vector(7 downto 0);
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-- firo
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Run_o : out std_logic;
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Data_i : in std_logic
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);
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end component FiRoCtrlE;
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component FiRoE is
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generic (
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IMP : string := "HDL",
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TOGGLE : boolean := true
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);
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port (
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FiRo_o : out std_logic;
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Run_i : in std_logic
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);
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end component FiRoE;
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--+ EFB SPI slave component
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component EfbSpiSlave is
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port (
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wb_clk_i : in std_logic;
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wb_rst_i : in std_logic;
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wb_cyc_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_we_i : in std_logic;
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wb_adr_i : in std_logic_vector(7 downto 0);
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wb_dat_i : in std_logic_vector(7 downto 0);
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wb_dat_o : out std_logic_vector(7 downto 0);
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wb_ack_o : out std_logic;
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spi_clk : inout std_logic;
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spi_miso : inout std_logic;
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spi_mosi : inout std_logic;
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spi_scsn : in std_logic;
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spi_irq : out std_logic
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);
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end component EfbSpiSlave;
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--+ oscillator component
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component OSCH is
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generic (
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NOM_FREQ : string := "26.60"
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);
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port (
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STDBY : in std_logic;
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OSC : out std_logic;
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SEDSTDBY : out std_logic
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);
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end component OSCH;
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attribute NOM_FREQ : string;
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attribute NOM_FREQ of i_OSC : label is "26.60";
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--+ system signals
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signal s_sys_clk : std_logic;
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signal s_sys_rst : std_logic := '1';
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signal s_spi_sclk : std_logic;
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signal s_spi_miso : std_logic;
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signal s_spi_mosi : std_logic;
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--+ Wishbone bus signals
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signal s_wb_clk : std_logic;
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signal s_wb_rst : std_logic;
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signal s_wb_cyc : std_logic;
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signal s_wb_stb : std_logic;
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signal s_wb_we : std_logic;
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signal s_wb_adr : std_logic_vector(7 downto 0);
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signal s_wb_master_dat : std_logic_vector(7 downto 0);
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signal s_wb_slave_dat : std_logic_vector(7 downto 0);
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signal s_wb_ack : std_logic;
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--+ EFB signals
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signal s_efb_irq : std_logic;
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--+ Wishbone master signals
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signal s_local_wen : std_logic;
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signal s_local_ren : std_logic;
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signal s_local_adr : std_logic_vector(7 downto 0);
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signal s_local_read_data : std_logic_vector(7 downto 0);
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signal s_local_write_data : std_logic_vector(7 downto 0);
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signal s_local_ack : std_logic;
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--+ RNG signals
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signal s_rng_start : std_logic;
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signal s_rng_wait : std_logic_vector(7 downto 0);
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signal s_rng_run : std_logic_vector(7 downto 0);
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signal s_rng_data_valid : std_logic;
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signal s_rng_data : std_logic_vector(7 downto 0);
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signal s_firo_run : std_logic;
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signal s_firo_data : std_logic;
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begin
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--+ Oscillator instance
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--+ It's generating our 26.6 MHz system lock
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i_OSC : OSCH
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generic map (
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NOM_FREQ => "26.60"
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)
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port map (
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STDBY => '0',
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OSC => s_sys_clk,
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SEDSTDBY => open
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);
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s_wb_clk <= s_sys_clk;
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s_wb_rst <= not(s_sys_rst);
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ResetP : process (s_sys_clk) is
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variable v_clk_count : natural range 0 to 15 := 15;
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begin
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if(rising_edge(s_sys_clk)) then
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if(v_clk_count = 0) then
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s_sys_rst <= '1';
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else
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s_sys_rst <= '0';
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v_clk_count := v_clk_count - 1;
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end if;
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end if;
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end process ResetP;
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--+ EFB SPI slave instance
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i_EfbSpiSlave : EfbSpiSlave
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port map (
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wb_clk_i => s_wb_clk,
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wb_rst_i => s_wb_rst,
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wb_cyc_i => s_wb_cyc,
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wb_stb_i => s_wb_stb,
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wb_we_i => s_wb_we,
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wb_adr_i => s_wb_adr,
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wb_dat_i => s_wb_master_dat,
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wb_dat_o => s_wb_slave_dat,
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wb_ack_o => s_wb_ack,
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spi_clk => SpiSclk_i,
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spi_miso => SpiMiso_o,
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spi_mosi => SpiMosi_i,
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spi_scsn => SpiSte_i,
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spi_irq => s_efb_irq
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);
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i_WishBoneMasterE : WishBoneMasterE
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generic map (
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G_ADR_WIDTH => 8,
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G_DATA_WIDTH => 8
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)
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port map (
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--+ wishbone system if
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WbRst_i => s_wb_rst,
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WbClk_i => s_wb_clk,
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--+ wishbone outputs
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WbCyc_o => s_wb_cyc,
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WbStb_o => s_wb_stb,
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WbWe_o => s_wb_we,
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WbAdr_o => s_wb_adr,
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WbDat_o => s_wb_master_dat,
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--+ wishbone inputs
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WbDat_i => s_wb_slave_dat,
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WbAck_i => s_wb_ack,
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WbErr_i => '0',
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--+ local register if
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LocalWen_i => s_local_wen,
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LocalRen_i => s_local_ren,
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LocalAdress_i => s_local_adr,
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LocalData_i => s_local_write_data,
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LocalData_o => s_local_read_data,
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LocalAck_o => s_local_ack,
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LocalError_o => open
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);
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i_RaspiFpgaCtrlE : RaspiFpgaCtrlE
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port map (
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--+ System if
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Rst_n_i => s_sys_rst,
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Clk_i => s_sys_clk,
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--+ local register if
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LocalWen_o => s_local_wen,
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LocalRen_o => s_local_ren,
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LocalAdress_o => s_local_adr,
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LocalData_i => s_local_read_data,
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LocalData_o => s_local_write_data,
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LocalAck_i => s_local_ack,
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LocalError_i => '0',
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--+ EFB if
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EfbSpiIrq_i => s_efb_irq,
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--+ RNG if
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RngStart_o => s_rng_start,
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RngWait_o => s_rng_wait,
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RngRun_o => s_rng_run,
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RngDataValid_i => s_rng_data_valid,
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RngData_i => s_rng_data
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);
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i_FiRoCtrlE : FiRoCtrlE
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generic map (
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EXTRACT => true
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)
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port map (
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--+ system if
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Clk_i => s_sys_clk,
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Reset_i => s_sys_rst,
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--+ ctrl/status
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Start_i => s_rng_start,
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Wait_i => s_rng_wait,
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Run_i => s_rng_run,
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--+ rnd data
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DataValid_o => s_rng_data_valid,
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Data_o => s_rng_data,
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-- firo
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Run_o => s_firo_run,
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Data_i => s_firo_data
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);
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i_FiRoE : FiRoE
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generic map (
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IMP => "LUT",
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TOGGLE => true
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)
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port map (
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FiRo_o => s_firo_data,
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Run_i => s_firo_run
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);
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RaspiIrq_o <= '0';
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end architecture rtl;
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