Various projects using Raspberry Pi

RaspiFpgaE.vhd 8.7KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library machxo2;
  5. use machxo2.components.all;
  6. entity RaspiFpgaE is
  7. port (
  8. --+ SPI slave if
  9. SpiSclk_i : inout std_logic;
  10. SpiSte_i : in std_logic;
  11. SpiMosi_i : inout std_logic;
  12. SpiMiso_o : inout std_logic;
  13. --* interrupt line to raspi
  14. RaspiIrq_o : out std_logic
  15. );
  16. end entity RaspiFpgaE;
  17. architecture rtl of RaspiFpgaE is
  18. --+ Wishbone master component
  19. component WishBoneMasterE is
  20. generic (
  21. G_ADR_WIDTH : positive := 8; --* address bus width
  22. G_DATA_WIDTH : positive := 8 --* data bus width
  23. );
  24. port (
  25. --+ wishbone system if
  26. WbRst_i : in std_logic;
  27. WbClk_i : in std_logic;
  28. --+ wishbone outputs
  29. WbCyc_o : out std_logic;
  30. WbStb_o : out std_logic;
  31. WbWe_o : out std_logic;
  32. WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
  33. WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  34. --+ wishbone inputs
  35. WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  36. WbAck_i : in std_logic;
  37. WbErr_i : in std_logic;
  38. --+ local register if
  39. LocalWen_i : in std_logic;
  40. LocalRen_i : in std_logic;
  41. LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
  42. LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  43. LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  44. LocalAck_o : out std_logic;
  45. LocalError_o : out std_logic
  46. );
  47. end component WishBoneMasterE;
  48. component RaspiFpgaCtrlE is
  49. port (
  50. --+ System if
  51. Rst_n_i : in std_logic;
  52. Clk_i : in std_logic;
  53. --+ local register if
  54. LocalWen_o : out std_logic;
  55. LocalRen_o : out std_logic;
  56. LocalAdress_o : out std_logic_vector(7 downto 0);
  57. LocalData_i : in std_logic_vector(7 downto 0);
  58. LocalData_o : out std_logic_vector(7 downto 0);
  59. LocalAck_i : in std_logic;
  60. LocalError_i : in std_logic;
  61. --+ EFB if
  62. EfbSpiIrq_i : in std_logic;
  63. --+ RNG if
  64. RngStart_o : out std_logic;
  65. RngWait_o : out std_logic_vector(7 downto 0);
  66. RngRun_o : out std_logic_vector(7 downto 0);
  67. RngDataValid_i : in std_logic;
  68. RngData_i : in std_logic_vector(7 downto 0)
  69. );
  70. end component RaspiFpgaCtrlE;
  71. component FiRoCtrlE is
  72. generic (
  73. EXTRACT : boolean := true
  74. );
  75. port (
  76. --+ system if
  77. Clk_i : in std_logic;
  78. Reset_i : in std_logic;
  79. --+ ctrl/status
  80. Start_i : in std_logic;
  81. Wait_i : in std_logic_vector(7 downto 0);
  82. Run_i : in std_logic_vector(7 downto 0);
  83. --+ rnd data
  84. DataValid_o : out std_logic;
  85. Data_o : out std_logic_vector(7 downto 0);
  86. -- firo
  87. Run_o : out std_logic;
  88. Data_i : in std_logic
  89. );
  90. end component FiRoCtrlE;
  91. component FiRoE is
  92. generic (
  93. IMP : string := "HDL",
  94. TOGGLE : boolean := true
  95. );
  96. port (
  97. FiRo_o : out std_logic;
  98. Run_i : in std_logic
  99. );
  100. end component FiRoE;
  101. --+ EFB SPI slave component
  102. component EfbSpiSlave is
  103. port (
  104. wb_clk_i : in std_logic;
  105. wb_rst_i : in std_logic;
  106. wb_cyc_i : in std_logic;
  107. wb_stb_i : in std_logic;
  108. wb_we_i : in std_logic;
  109. wb_adr_i : in std_logic_vector(7 downto 0);
  110. wb_dat_i : in std_logic_vector(7 downto 0);
  111. wb_dat_o : out std_logic_vector(7 downto 0);
  112. wb_ack_o : out std_logic;
  113. spi_clk : inout std_logic;
  114. spi_miso : inout std_logic;
  115. spi_mosi : inout std_logic;
  116. spi_scsn : in std_logic;
  117. spi_irq : out std_logic
  118. );
  119. end component EfbSpiSlave;
  120. --+ oscillator component
  121. component OSCH is
  122. generic (
  123. NOM_FREQ : string := "26.60"
  124. );
  125. port (
  126. STDBY : in std_logic;
  127. OSC : out std_logic;
  128. SEDSTDBY : out std_logic
  129. );
  130. end component OSCH;
  131. attribute NOM_FREQ : string;
  132. attribute NOM_FREQ of i_OSC : label is "26.60";
  133. --+ system signals
  134. signal s_sys_clk : std_logic;
  135. signal s_sys_rst : std_logic := '1';
  136. signal s_spi_sclk : std_logic;
  137. signal s_spi_miso : std_logic;
  138. signal s_spi_mosi : std_logic;
  139. --+ Wishbone bus signals
  140. signal s_wb_clk : std_logic;
  141. signal s_wb_rst : std_logic;
  142. signal s_wb_cyc : std_logic;
  143. signal s_wb_stb : std_logic;
  144. signal s_wb_we : std_logic;
  145. signal s_wb_adr : std_logic_vector(7 downto 0);
  146. signal s_wb_master_dat : std_logic_vector(7 downto 0);
  147. signal s_wb_slave_dat : std_logic_vector(7 downto 0);
  148. signal s_wb_ack : std_logic;
  149. --+ EFB signals
  150. signal s_efb_irq : std_logic;
  151. --+ Wishbone master signals
  152. signal s_local_wen : std_logic;
  153. signal s_local_ren : std_logic;
  154. signal s_local_adr : std_logic_vector(7 downto 0);
  155. signal s_local_read_data : std_logic_vector(7 downto 0);
  156. signal s_local_write_data : std_logic_vector(7 downto 0);
  157. signal s_local_ack : std_logic;
  158. --+ RNG signals
  159. signal s_rng_start : std_logic;
  160. signal s_rng_wait : std_logic_vector(7 downto 0);
  161. signal s_rng_run : std_logic_vector(7 downto 0);
  162. signal s_rng_data_valid : std_logic;
  163. signal s_rng_data : std_logic_vector(7 downto 0);
  164. signal s_firo_run : std_logic;
  165. signal s_firo_data : std_logic;
  166. begin
  167. --+ Oscillator instance
  168. --+ It's generating our 26.6 MHz system lock
  169. i_OSC : OSCH
  170. generic map (
  171. NOM_FREQ => "26.60"
  172. )
  173. port map (
  174. STDBY => '0',
  175. OSC => s_sys_clk,
  176. SEDSTDBY => open
  177. );
  178. s_wb_clk <= s_sys_clk;
  179. s_wb_rst <= not(s_sys_rst);
  180. ResetP : process (s_sys_clk) is
  181. variable v_clk_count : natural range 0 to 15 := 15;
  182. begin
  183. if(rising_edge(s_sys_clk)) then
  184. if(v_clk_count = 0) then
  185. s_sys_rst <= '1';
  186. else
  187. s_sys_rst <= '0';
  188. v_clk_count := v_clk_count - 1;
  189. end if;
  190. end if;
  191. end process ResetP;
  192. --+ EFB SPI slave instance
  193. i_EfbSpiSlave : EfbSpiSlave
  194. port map (
  195. wb_clk_i => s_wb_clk,
  196. wb_rst_i => s_wb_rst,
  197. wb_cyc_i => s_wb_cyc,
  198. wb_stb_i => s_wb_stb,
  199. wb_we_i => s_wb_we,
  200. wb_adr_i => s_wb_adr,
  201. wb_dat_i => s_wb_master_dat,
  202. wb_dat_o => s_wb_slave_dat,
  203. wb_ack_o => s_wb_ack,
  204. spi_clk => SpiSclk_i,
  205. spi_miso => SpiMiso_o,
  206. spi_mosi => SpiMosi_i,
  207. spi_scsn => SpiSte_i,
  208. spi_irq => s_efb_irq
  209. );
  210. i_WishBoneMasterE : WishBoneMasterE
  211. generic map (
  212. G_ADR_WIDTH => 8,
  213. G_DATA_WIDTH => 8
  214. )
  215. port map (
  216. --+ wishbone system if
  217. WbRst_i => s_wb_rst,
  218. WbClk_i => s_wb_clk,
  219. --+ wishbone outputs
  220. WbCyc_o => s_wb_cyc,
  221. WbStb_o => s_wb_stb,
  222. WbWe_o => s_wb_we,
  223. WbAdr_o => s_wb_adr,
  224. WbDat_o => s_wb_master_dat,
  225. --+ wishbone inputs
  226. WbDat_i => s_wb_slave_dat,
  227. WbAck_i => s_wb_ack,
  228. WbErr_i => '0',
  229. --+ local register if
  230. LocalWen_i => s_local_wen,
  231. LocalRen_i => s_local_ren,
  232. LocalAdress_i => s_local_adr,
  233. LocalData_i => s_local_write_data,
  234. LocalData_o => s_local_read_data,
  235. LocalAck_o => s_local_ack,
  236. LocalError_o => open
  237. );
  238. i_RaspiFpgaCtrlE : RaspiFpgaCtrlE
  239. port map (
  240. --+ System if
  241. Rst_n_i => s_sys_rst,
  242. Clk_i => s_sys_clk,
  243. --+ local register if
  244. LocalWen_o => s_local_wen,
  245. LocalRen_o => s_local_ren,
  246. LocalAdress_o => s_local_adr,
  247. LocalData_i => s_local_read_data,
  248. LocalData_o => s_local_write_data,
  249. LocalAck_i => s_local_ack,
  250. LocalError_i => '0',
  251. --+ EFB if
  252. EfbSpiIrq_i => s_efb_irq,
  253. --+ RNG if
  254. RngStart_o => s_rng_start,
  255. RngWait_o => s_rng_wait,
  256. RngRun_o => s_rng_run,
  257. RngDataValid_i => s_rng_data_valid,
  258. RngData_i => s_rng_data
  259. );
  260. i_FiRoCtrlE : FiRoCtrlE
  261. generic map (
  262. EXTRACT => true
  263. )
  264. port map (
  265. --+ system if
  266. Clk_i => s_sys_clk,
  267. Reset_i => s_sys_rst,
  268. --+ ctrl/status
  269. Start_i => s_rng_start,
  270. Wait_i => s_rng_wait,
  271. Run_i => s_rng_run,
  272. --+ rnd data
  273. DataValid_o => s_rng_data_valid,
  274. Data_o => s_rng_data,
  275. -- firo
  276. Run_o => s_firo_run,
  277. Data_i => s_firo_data
  278. );
  279. i_FiRoE : FiRoE
  280. generic map (
  281. IMP => "LUT",
  282. TOGGLE => true
  283. )
  284. port map (
  285. FiRo_o => s_firo_data,
  286. Run_i => s_firo_run
  287. );
  288. RaspiIrq_o <= '0';
  289. end architecture rtl;