new folder 'cpld' with test project to test the CPLD on USB-AVR-CPLD

* sim/makefile with targets to simulate the cpld design
* sim/cpldtestt.vhd file with the testbench
* sim/cpldtestt.tcl file with control commands for gtkwave
* src/cpldteste.vhd file with test design (@ the moment a simple 10101 @ gpio port)
* syn/constraints/cpldtest.ucf with implementation constraints
* syn/makefile with targets to build the cpld design

cpld/sim/cpldtestt.tcl

@@ -0,0 +1,4 @@
+set signals [list]
+lappend signals "top.cpldtestt.s_cpld_clk"
+lappend signals "top.cpldtestt.s_cpld_gpio"
+set num_added [ gtkwave::addSignalsFromList $signals ]

cpld/sim/cpldtestt.vhd

@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity CpldTestT is
+end entity CpldTestT;
+
+
+architecture rtl of CpldTestT is
+
+
+  component CpldTestE is
+    port (
+      -- globals
+      XcClk_i    : in    std_logic;
+      -- avr
+      AvrData_io : inout std_logic_vector(13 downto 0);
+      AvrSck_i   : in    std_logic;
+      AvrMosi_i  : in    std_logic;
+      AvrMiso_o  : out   std_logic;
+      -- spi flash
+      SpfRst_n_o : out   std_logic;
+      SpfCs_n_o  : out   std_logic;
+      SpfSck_o   : out   std_logic;
+      SpfMosi_o  : out   std_logic;
+      SpfMiso_i  : in    std_logic;
+      -- gpio
+      Gpio_io    : inout std_logic_vector(4 downto 0)
+    );
+  end component CpldTestE;
+
+  signal s_cpld_clk  : std_logic := '0';
+  signal s_cpld_gpio : std_logic_vector(4 downto 0);
+
+begin
+
+
+  s_cpld_clk <= not(s_cpld_clk) after 20 ns;
+
+  i_CpldTestE : CpldTestE
+  port map
+    (
+      -- globals
+      XcClk_i    => s_cpld_clk,
+      -- avr
+      AvrData_io => open,
+      AvrSck_i   => '0',
+      AvrMosi_i  => '0',
+      AvrMiso_o  => open,
+      -- spi flash
+      SpfRst_n_o => open,
+      SpfCs_n_o  => open,
+      SpfSck_o   => open,
+      SpfMosi_o  => open,
+      SpfMiso_i  => '0',
+      -- gpio
+      Gpio_io    => s_cpld_gpio
+    );
+
+
+end architecture rtl;

cpld/sim/makefile

@@ -0,0 +1,24 @@
+PROJECT = cpldtestt
+
+MAKE_WORKDIR := $(shell mkdir -p work)
+
+WORKDIR = ${CURDIR}/work
+
+all : sim wave
+
+.PHONY:
+sim : $(PROJECT).ghw
+
+
+$(PROJECT).ghw : ../src/*.vhd $(PROJECT).vhd
+	cd $(WORKDIR); ghdl -a ../../src/*.vhd ../$(PROJECT).vhd
+	cd $(WORKDIR); ghdl -e $(PROJECT)
+	cd $(WORKDIR); ghdl -r $(PROJECT) --wave=../$(PROJECT).ghw --assert-level=error --stop-time=150us
+
+wave : $(PROJECT).ghw $(PROJECT).tcl
+	gtkwave -T $(PROJECT).tcl $(PROJECT).ghw
+	
+clean :
+	echo "# cleaning simulation files"
+	rm -f $(PROJECT).ghw
+	rm -rf $(WORKDIR)

cpld/src/cpldteste.vhd

@@ -0,0 +1,37 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+
+entity CpldTestE is
+  port (
+    -- globals
+    XcClk_i    : in    std_logic;
+    -- avr
+    AvrData_io : inout std_logic_vector(13 downto 0);
+    AvrSck_i   : in    std_logic;
+    AvrMosi_i  : in    std_logic;
+    AvrMiso_o  : out   std_logic;
+    -- spi flash
+    SpfRst_n_o : out   std_logic;
+    SpfCs_n_o  : out   std_logic;
+    SpfSck_o   : out   std_logic;
+    SpfMosi_o  : out   std_logic;
+    SpfMiso_i  : in    std_logic;
+    -- gpio
+    Gpio_io    : inout std_logic_vector(4 downto 0)
+  );
+end entity CpldTestE;
+
+
+architecture rtl of CpldTestE is
+
+
+begin
+
+
+  -- test gpio pins
+  Gpio_io <= "10101";
+
+
+end architecture rtl;

cpld/syn/constraints/cpldtest.ucf

@@ -0,0 +1,34 @@
+# pin locations
+XcClk_i        LOC = PIN43; 
+AvrData_io<0>  LOC = PIN6;
+AvrData_io<1>  LOC = PIN5;
+AvrData_io<2>  LOC = PIN3;
+AvrData_io<3>  LOC = PIN34;
+AvrData_io<4>  LOC = PIN33;
+AvrData_io<5>  LOC = PIN32;
+AvrData_io<6>  LOC = PIN31;
+AvrData_io<7>  LOC = PIN30;
+AvrData_io<8>  LOC = PIN29;
+AvrData_io<9>  LOC = PIN28;
+AvrData_io<10> LOC = PIN27;
+AvrData_io<11> LOC = PIN23;
+AvrData_io<12> LOC = PIN12;
+AvrData_io<13> LOC = PIN8;
+AvrData_io<14> LOC = PIN7;
+AvrSck_i       LOC = PIN44;
+AvrMosi_i      LOC = PIN2;
+AvrMiso_o      LOC = PIN1;
+SpfRst_n_o     LOC = PIN21;
+SpfCs_n_o      LOC = PIN22;
+SpfSck_o       LOC = PIN20;
+SpfMosi_o      LOC = PIN13;
+SpfMiso_i      LOC = PIN14;
+Gpio_io<0>     LOC = PIN42;
+Gpio_io<1>     LOC = PIN41;
+Gpio_io<2>     LOC = PIN40;
+Gpio_io<3>     LOC = PIN39;
+Gpio_io<4>     LOC = PIN38;
+
+# clock timing
+NET "XcClk_i" TNM_NET = XcClk_i;
+TIMESPEC TS_Clk_i = PERIOD "XcClk_i" 40 ns HIGH 50%;