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wrapped gpio pin test code with a a synchronious process, sensitive to XcClk_i

T. Meissner 8 years ago
parent
commit
cb4a735e25
1 changed files with 11 additions and 2 deletions
  1. 11
    2
      cpld/src/cpldteste.vhd

+ 11
- 2
cpld/src/cpldteste.vhd View File

@@ -8,7 +8,7 @@ entity CpldTestE is
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     -- globals
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     XcClk_i    : in    std_logic;
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     -- avr
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-    AvrData_io : inout std_logic_vector(13 downto 0);
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+    AvrData_io : inout std_logic_vector(14 downto 0);
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     AvrSck_i   : in    std_logic;
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     AvrMosi_i  : in    std_logic;
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     AvrMiso_o  : out   std_logic;
@@ -31,7 +31,16 @@ begin
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   -- test gpio pins
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-  Gpio_io <= "10101";
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+  process (XcClk_i) is
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+  begin
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+    if(rising_edge(XcClk_i)) then
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+      if(AvrData_io(0) = '0') then
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+        Gpio_io <= "00000";
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+      else
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+        Gpio_io <= "10101";
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+      end if;
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+    end if;
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+  end process;
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 end architecture rtl;