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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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library std; |
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use std.env.all; |
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library osvvm; |
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use osvvm.NamePkg.all ; |
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use osvvm.TranscriptPkg.all ; |
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use osvvm.OsvvmGlobalPkg.all ; |
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use osvvm.AlertLogPkg.all ; |
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use osvvm.RandomPkg.all ; |
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use osvvm.CoveragePkg.all ; |
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use osvvm.MemoryPkg.all ; |
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entity osvvm_fsm_coverage is |
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end entity osvvm_fsm_coverage; |
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architecture sim of osvvm_fsm_coverage is |
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type t_fsm_state is (IDLE, ADDR, DATA); |
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signal s_fsm_state : t_fsm_state; |
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signal s_clk : std_logic := '0'; |
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signal s_reset_n : std_logic := '0'; |
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shared variable sv_cover : CovPType; |
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procedure fsm_covadd_states (name : in string; |
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prev : in t_fsm_state; |
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curr : in t_fsm_state; |
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covdb : inout CovPType) is |
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begin |
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covdb.AddCross(name, |
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GenBin(t_fsm_state'pos(prev)), |
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GenBin(t_fsm_state'pos(curr))); |
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wait; |
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end procedure fsm_covadd_states; |
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procedure fsm_covadd_illegal (name : in string; |
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covdb : inout CovPType) is |
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begin |
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covdb.AddCross(ALL_ILLEGAL, ALL_ILLEGAL); |
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wait; |
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end procedure fsm_covadd_illegal; |
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procedure fsm_covcollect (signal reset : in std_logic; |
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signal clk : in std_logic; |
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signal state : in t_fsm_state; |
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covdb : inout CovPType) is |
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variable v_state : t_fsm_state := t_fsm_state'left; |
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begin |
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wait until reset = '1' and rising_edge(clk); |
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loop |
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v_state := state; |
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wait until rising_edge(s_clk); |
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covdb.ICover((t_fsm_state'pos(v_state), t_fsm_state'pos(state))); |
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end loop; |
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end procedure fsm_covcollect; |
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begin |
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s_clk <= not(s_clk) after 5 ns; |
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s_reset_n <= '1' after 20 ns; |
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FsmP : process (s_reset_n, s_clk) is |
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begin |
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if (s_reset_n = '0') then |
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s_fsm_state <= IDLE; |
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elsif (rising_edge(s_clk)) then |
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case s_fsm_state is |
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when IDLE => s_fsm_state <= ADDR; |
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when ADDR => s_fsm_state <= DATA; |
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when DATA => s_fsm_state <= IDLE; |
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when others => |
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null; |
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end case; |
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end if; |
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end process FsmP; |
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fsm_covadd_states ("IDLE->ADDR", IDLE, ADDR, sv_cover); |
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fsm_covadd_states ("ADDR->DATA", ADDR, DATA, sv_cover); |
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fsm_covadd_states ("DATA->IDLE", DATA, IDLE, sv_cover); |
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fsm_covadd_illegal ("ILLEGAL", sv_cover); |
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fsm_covcollect (s_reset_n, s_clk, s_fsm_state, sv_cover); |
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FinishP : process is |
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begin |
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wait until s_clk'active; |
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if (sv_cover.IsCovered) then |
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Log("FSM full covered :)", ALWAYS); |
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sv_cover.SetName("FSM state coverage report"); |
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sv_cover.WriteBin; |
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stop(0); |
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end if; |
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end process FinishP; |
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-- psl default clock is rising_edge(s_clk); |
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-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE) -> next (s_fsm_state = ADDR) abort not(s_reset_n); |
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-- psl ADDR_DATA : assert always (s_fsm_state = ADDR) -> next (s_fsm_state = DATA) abort not(s_reset_n); |
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-- psl DATA_IDLE : assert always (s_fsm_state = DATA) -> next (s_fsm_state = IDLE) abort not(s_reset_n); |
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end architecture sim; |