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@ -112,9 +112,14 @@ begin |
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-- psl default clock is rising_edge(s_clk); |
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-- psl default clock is rising_edge(s_clk); |
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-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE) -> next (s_fsm_state = ADDR) abort not(s_reset_n); |
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-- psl ADDR_DATA : assert always (s_fsm_state = ADDR) -> next (s_fsm_state = DATA) abort not(s_reset_n); |
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-- psl DATA_IDLE : assert always (s_fsm_state = DATA) -> next (s_fsm_state = IDLE) abort not(s_reset_n); |
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-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n) |
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-- report "FSM error: IDLE should be followed by ADDR state"; |
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-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n); |
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-- report "FSM error: ADDR should be followed by DATA state"; |
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-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n); |
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-- report "FSM error: DATA should be followed by IDLE state"; |
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end architecture sim; |
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end architecture sim; |