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Add testcase for evaluating PSL endpoints in VHDL code

T. Meissner 3 years ago
parent
commit
ad80c4c082

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psl_endpoint_eval_in_vhdl/Makefile View File

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+.PHONY: sim compile clean wave
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+
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+
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+sim \
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+work/psl_endpoint_eval_in_vhdl \
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+work/psl_endpoint_eval_in_vhdl.ghw: work/psl_endpoint_eval_in_vhdl.o log
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+	@echo Run test ...
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+	@cd work; ghdl -r --std=08 -fpsl psl_endpoint_eval_in_vhdl \
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+	                  --psl-report=../log/psl_endpoint_eval_in_vhdl.json \
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+	                  --wave=../log/psl_endpoint_eval_in_vhdl.ghw \
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+	                  --stop-time=200ns
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+
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+
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+compile \
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+work/psl_endpoint_eval_in_vhdl.o: psl_endpoint_eval_in_vhdl.vhd work
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+	@echo "Analyse & elaborate test ..."
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+	cd work; ghdl -a --std=08 -fpsl ../psl_endpoint_eval_in_vhdl.vhd
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+	cd work; ghdl -e --std=08 -fpsl psl_endpoint_eval_in_vhdl >& /dev/null
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+
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+
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+wave: work/psl_endpoint_eval_in_vhdl.ghw
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+	@echo Run waveform viewer ...
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+	@gtkwave log/psl_endpoint_eval_in_vhdl.ghw -S psl_endpoint_eval_in_vhdl.tcl &
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+
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+
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+work \
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+log:
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+	mkdir $@
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+
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+
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+clean:
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+	@echo Remove generated files ...
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+	@rm -rf work log

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psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd View File

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+library ieee;
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+use ieee.std_logic_1164.all;
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+use ieee.numeric_std.all;
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+
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+library std;
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+use std.env.all;
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+
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+
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+
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+entity psl_endpoint_eval_in_vhdl is
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+end entity psl_endpoint_eval_in_vhdl;
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+
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+
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+
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+architecture test of psl_endpoint_eval_in_vhdl is
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+
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+
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+  signal s_rst_n : std_logic := '0';
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+  signal s_clk   : std_logic := '0';
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+  signal s_write : std_logic;
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+  signal s_read  : std_logic;
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+
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+
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+begin
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+
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+
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+  s_rst_n <= '1' after 100 ns;
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+  s_clk   <= not s_clk after 10 ns;
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+
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+
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+  TestP : process is
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+  begin
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+    report "RUNNING psl_endpoint_eval_in_vhdl test case";
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+    report "==========================================";
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+    s_write <= '0';  -- named assertion should hit
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+    s_read  <= '0';
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+    wait until s_rst_n = '1' and rising_edge(s_clk);
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+    s_write <= '1';
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+    wait until rising_edge(s_clk);
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+    s_read  <= '1';  -- assertion should hit
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+    wait until rising_edge(s_clk);
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+    s_write <= '0';
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+    s_read  <= '0';
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+    wait until rising_edge(s_clk);
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+    stop(0);
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+    wait;
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+  end process TestP;
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+
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+
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+  -- psl default clock is rising_edge(s_clk);
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+  -- psl endpoint E_TEST0 is {not(s_write); s_write};
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+
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+
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+  process is
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+  begin
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+    wait for E_TEST0;
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+    report "HIT";
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+    wait;
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+  end process;
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+
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+
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+end architecture test;