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125 lines
3.2 KiB
125 lines
3.2 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library std;
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use std.env.all;
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library osvvm;
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use osvvm.NamePkg.all ;
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use osvvm.TranscriptPkg.all ;
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use osvvm.OsvvmGlobalPkg.all ;
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use osvvm.AlertLogPkg.all ;
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use osvvm.RandomPkg.all ;
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use osvvm.CoveragePkg.all ;
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use osvvm.MemoryPkg.all ;
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entity osvvm_fsm_psl_coverage is
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end entity osvvm_fsm_psl_coverage;
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architecture sim of osvvm_fsm_psl_coverage is
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type t_fsm_state is (IDLE, ADDR, DATA);
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signal s_fsm_state : t_fsm_state;
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signal s_clk : std_logic := '0';
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signal s_reset_n : std_logic := '0';
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signal s_state_cover : unsigned(2 downto 0);
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shared variable sv_cover : CovPType;
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begin
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s_clk <= not(s_clk) after 5 ns;
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s_reset_n <= '1' after 20 ns;
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FsmP : process (s_reset_n, s_clk) is
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begin
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if (s_reset_n = '0') then
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s_fsm_state <= IDLE;
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elsif (rising_edge(s_clk)) then
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case s_fsm_state is
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when IDLE => s_fsm_state <= ADDR;
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when ADDR => s_fsm_state <= DATA;
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when DATA => s_fsm_state <= IDLE;
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when others =>
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null;
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end case;
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end if;
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end process FsmP;
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-- psl endpoint E_IDLE_ADDR is {s_fsm_state = IDLE; s_fsm_state = ADDR}@s_clk'active;
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-- psl endpoint E_ADDR_DATA is {s_fsm_state = ADDR; s_fsm_state = DATA}@s_clk'active;
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-- psl endpoint E_DATA_IDLE is {s_fsm_state = DATA; s_fsm_state = IDLE}@s_clk'active;
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EndpointRegP : process is
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begin
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s_state_cover <= (others => '0');
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if (E_IDLE_ADDR) then
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s_state_cover(0) <= '1';
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end if;
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if (E_ADDR_DATA) then
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s_state_cover(1) <= '1';
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end if;
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if (E_DATA_IDLE) then
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s_state_cover(2) <= '1';
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end if;
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wait until rising_edge(s_clk);
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end process;
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sv_cover.AddBins("IDLE->ADDR", GenBin(1));
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sv_cover.AddBins("ADDR->DATA", GenBin(2));
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sv_cover.AddBins("DATA->IDLE", GenBin(4));
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sv_cover.AddBins(ALL_ILLEGAL);
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CovCollectP : process is
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begin
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wait until s_reset_n = '1' and rising_edge(s_clk);
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-- we have to wait another cycle because endpoints are delayed by one cycle
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-- if we don't wait, we get an illegal BIN hit in second cycle after released reset
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wait until rising_edge(s_clk);
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loop
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wait until rising_edge(s_clk);
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sv_cover.ICover(to_integer(s_state_cover));
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end loop;
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end process CovCollectP;
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FinishP : process is
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begin
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wait until s_clk'active;
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if (sv_cover.IsCovered) then
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Log("FSM full covered :)", ALWAYS);
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sv_cover.SetName("FSM state coverage report");
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sv_cover.WriteBin;
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stop(0);
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end if;
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end process FinishP;
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-- psl default clock is rising_edge(s_clk);
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-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n)
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-- report "FSM error: IDLE should be followed by ADDR state";
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-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n);
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-- report "FSM error: ADDR should be followed by DATA state";
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-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n);
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-- report "FSM error: DATA should be followed by IDLE state";
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end architecture sim;
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