Examples and design pattern for VHDL verification
vhdl
osvvm
fpga
ghdl
testbenches
psl
coverage

Makefile 896B

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  1. .PHONY: sim compile clean wave
  2. sim \
  3. work/psl_endpoint_eval_in_vhdl \
  4. work/psl_endpoint_eval_in_vhdl.ghw: work/psl_endpoint_eval_in_vhdl.o log
  5. @echo Run test ...
  6. @cd work; ghdl -r --std=08 -fpsl psl_endpoint_eval_in_vhdl \
  7. --psl-report=../log/psl_endpoint_eval_in_vhdl.json \
  8. --wave=../log/psl_endpoint_eval_in_vhdl.ghw \
  9. --stop-time=200ns
  10. compile \
  11. work/psl_endpoint_eval_in_vhdl.o: psl_endpoint_eval_in_vhdl.vhd work
  12. @echo "Analyse & elaborate test ..."
  13. cd work; ghdl -a --std=08 -fpsl ../psl_endpoint_eval_in_vhdl.vhd
  14. cd work; ghdl -e --std=08 -fpsl psl_endpoint_eval_in_vhdl >& /dev/null
  15. wave: work/psl_endpoint_eval_in_vhdl.ghw
  16. @echo Run waveform viewer ...
  17. @gtkwave log/psl_endpoint_eval_in_vhdl.ghw -S psl_endpoint_eval_in_vhdl.tcl &
  18. work \
  19. log:
  20. mkdir $@
  21. clean:
  22. @echo Remove generated files ...
  23. @rm -rf work log