Examples and design pattern for VHDL verification
vhdl
osvvm
fpga
ghdl
testbenches
psl
coverage

psl_endpoint_eval_in_vhdl.vhd 1.3KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library std;
  5. use std.env.all;
  6. entity psl_endpoint_eval_in_vhdl is
  7. end entity psl_endpoint_eval_in_vhdl;
  8. architecture test of psl_endpoint_eval_in_vhdl is
  9. signal s_rst_n : std_logic := '0';
  10. signal s_clk : std_logic := '0';
  11. signal s_write : std_logic;
  12. signal s_read : std_logic;
  13. signal s_test0 : boolean;
  14. begin
  15. s_rst_n <= '1' after 100 ns;
  16. s_clk <= not s_clk after 10 ns;
  17. TestP : process is
  18. begin
  19. report "RUNNING psl_endpoint_eval_in_vhdl test case";
  20. report "==========================================";
  21. s_write <= '0'; -- named assertion should hit
  22. s_read <= '0';
  23. wait until s_rst_n = '1' and rising_edge(s_clk);
  24. s_write <= '1';
  25. wait until rising_edge(s_clk);
  26. s_read <= '1'; -- assertion should hit
  27. wait until rising_edge(s_clk);
  28. s_write <= '0';
  29. s_read <= '0';
  30. wait until rising_edge(s_clk);
  31. stop(0);
  32. wait;
  33. end process TestP;
  34. -- psl default clock is rising_edge(s_clk);
  35. -- psl endpoint E_TEST0 is {not(s_write); s_write};
  36. process is
  37. begin
  38. wait until E_TEST0;
  39. report "HIT";
  40. wait;
  41. end process;
  42. process is
  43. begin
  44. wait until rising_edge(s_clk);
  45. if (E_TEST0) then
  46. s_test0 <= true;
  47. else
  48. s_test0 <= false;
  49. end if;
  50. end process;
  51. end architecture test;