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70 lines
1.8 KiB
70 lines
1.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library std;
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use std.env.all;
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entity psl_test_endpoint is
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end entity psl_test_endpoint;
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architecture test of psl_test_endpoint is
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signal s_rst_n : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_write : std_logic;
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signal s_read : std_logic;
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begin
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s_rst_n <= '1' after 100 ns;
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s_clk <= not s_clk after 10 ns;
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TestP : process is
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begin
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report "RUNNING psl_test_endpoint test case";
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report "==========================================";
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s_write <= '0'; -- named assertion should hit
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s_read <= '0';
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wait until s_rst_n = '1' and rising_edge(s_clk);
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s_write <= '1';
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wait until rising_edge(s_clk);
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s_read <= '1'; -- assertion should hit
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wait until rising_edge(s_clk);
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s_write <= '0';
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s_read <= '0';
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wait until rising_edge(s_clk);
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--stop(0);
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wait;
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end process TestP;
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-- psl default clock is rising_edge(s_clk);
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-- psl endpoint E_TEST0 is {not(s_write); s_write};
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-- psl endpoint E_TEST1 is {s_write; s_write and not(s_read)};
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-- psl sequence abc_seq is {not(s_write); s_write};
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-- ASSERT0 should be passed, but not failed
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-- ASSERT1 should be failed
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-- ASSERT2 should not be passed
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-- psl ASSERT0 : assert always {E_TEST0} |=> {s_read} report "ASSERT0";
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-- psl ASSERT1 : assert always {E_TEST0} |-> {s_read} report "ASSERT1";
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-- psl ASSERT2 : assert always {E_TEST1} |-> {s_read} report "ASSERT2";
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-- COVERAGE0..COVERAGE2 should all hit @ same time
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-- COVERAGE3 should never hit
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-- psl COVERAGE0 : cover {not(s_write); s_write} report "COVERED0";
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-- psl COVERAGE1 : cover {abc_seq} report "COVERED1";
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-- psl COVERAGE2 : cover {E_TEST0} report "COVERED2";
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-- psl COVERAGE3 : cover {E_TEST1} report "COVERED3";
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end architecture test;
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