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tmeissner / formal_hw_verification
VHDL 0 0

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl
verilog
systemverilog
sva
assertions
formal
yosys

Updated 1 year ago

tmeissner / cryptocores
VHDL 0 0

cryptography ip-cores in vhdl / verilog

vhdl
osvvm
fpga
ghdl
testbenches
verilog
cryptography

Updated 4 years ago