Browse Source

Initial commit

T. Meissner 5 months ago
commit
b0d52f1534
4 changed files with 124 additions and 0 deletions
  1. 30
    0
      symbiotic_01/Makefile
  2. 37
    0
      symbiotic_01/Properties.sv
  3. 37
    0
      symbiotic_01/TestDesign.vhd
  4. 20
    0
      symbiotic_01/symbiyosys.sby

+ 30
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symbiotic_01/Makefile View File

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+SYMBI_SRC_FILE := /opt/symbiotic.sh
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+
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+TASKS := flag_check
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+
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+
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+.PHONY: all
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+all: flag_check
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+
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+
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+define taskTemplate
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+
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+.PHONY: $(1)
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+$(1):
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+	source $(SYMBI_SRC_FILE); sby -f symbiyosys.sby $(1)
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+
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+endef
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+
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+$(foreach task, $(TASKS), $(eval $(call taskTemplate,$(task))))
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+
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+
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+wave:
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+ifndef wf
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+	$(error please give wave parameter)
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+endif
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+	gtkwave -a trace.gtkw $(wf)
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+
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+
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+.PHONY: clean
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+clean:
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+	rm -rf symbiyosys_*

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symbiotic_01/Properties.sv View File

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+module Properties (
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+  // global
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+  input        clk,
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+  input        resetn,
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+  input  [1:0] sel,
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+  input  [3:0] we
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+);
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+
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+
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+  // Constrain reset
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+
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+  reg init_flag = 1;
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+
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+  always @(*) begin
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+    if (init_flag) assume (!resetn);
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+    if (!init_flag) assume (resetn);
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+  end
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+
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+  always @(posedge clk)
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+    init_flag <= 0;
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+
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+
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+  default clocking
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+    @(posedge clk);
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+  endclocking
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+
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+  default disable iff (!resetn);
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+
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+
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+  assert property (we[0] |=> sel == 0);
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+
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+
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+endmodule
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+
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+
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+
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+bind TestDesign Properties i_Properties (.*);

+ 37
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symbiotic_01/TestDesign.vhd View File

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+library ieee;
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+  use ieee.std_logic_1164.all;
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+  use ieee.numeric_std.all;
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+
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+
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+
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+entity TestDesign is
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+  port (
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+    clk    : in  std_logic;
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+    resetn : in  std_logic;
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+    sel    : in  std_logic_vector(1 downto 0);
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+    we     : out std_logic_vector(3 downto 0)
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+  );
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+end entity TestDesign;
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+
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+
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+
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+architecture rtl of TestDesign is
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+
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+
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+begin
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+
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+
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+  process (CLK, RESETn) is
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+  begin
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+    if (RESETn = '0') then
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+      we <= (others => '0');
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+    elsif (rising_edge(CLK)) then
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+      we(0) <= '0' when sel = "00" else '1';
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+      we(1) <= '0' when sel = "01" else '1';
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+      we(2) <= '0' when sel = "10" else '1';
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+      we(3) <= '0' when sel = "11" else '1';
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+    end if;
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+  end process;
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+
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+
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+end architecture;

+ 20
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symbiotic_01/symbiyosys.sby View File

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+[tasks]
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+flag_check
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+
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+[options]
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+mode prove
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+depth 30
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+
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+[engines]
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+abc pdr
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+
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+[script]
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+verific -vhdl TestDesign.vhd
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+verific -sv   Properties.sv
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+verific -import -extnets -all TestDesign
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+prep -top TestDesign
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+setundef -anyseq -undriven
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+
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+[files]
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+Properties.sv
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+TestDesign.vhd