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Switch to submodule repos instead of local clones

master
T. Meissner 3 years ago
parent
commit
1ebfafd654
4 changed files with 12 additions and 13 deletions
  1. +0
    -2
      .gitignore
  2. +6
    -0
      README.md
  3. +0
    -8
      env-setup.sh
  4. +6
    -3
      tests/Makefile

+ 0
- 2
.gitignore View File

@ -1,3 +1 @@
cryptocores
libvhdl
cocotbext-wishbone

+ 6
- 0
README.md View File

@ -15,6 +15,12 @@ Have fun!
## Quickstart guide
### Dependencies
*cocotb_with_ghdl* uses external libraries to get the components to verify. They are shipped as git submodules. You have to use the `--recursive` option when clone
the *cocotb_with_ghdl* repository to get them: `git clone --recursive https://git.goodcleanfun.de/tmeissner/cocotb_with_ghdl`
Another useful tool is GTKWave, install it if you want to use the waveform files generated by some of the tests.
### Change into docker container & install requirements
```


+ 0
- 8
env-setup.sh View File

@ -5,11 +5,3 @@ if [ ! -d cocotbext-wishbone/.git ]; then
cd cocotbext-wishbone && patch < ../setup.py.patch
cd ..
fi
if [ ! -d libvhdl/.git ]; then
git clone https://github.com/tmeissner/libvhdl.git
fi
if [ ! -d cryptocores/.git ]; then
git clone https://github.com/tmeissner/cryptocores.git
fi

+ 6
- 3
tests/Makefile View File

@ -1,6 +1,9 @@
# Default test
DUT ?= uarttx
# Path to ext deps
EXT := ../ext
ifeq (${DUT}, wishbone)
TOPLEVEL := wishboneslavee
SIM_ARGS := -gSimulation=true \
@ -13,9 +16,9 @@ endif
# Simulator (GHDL) & RTL related
SIM := ghdl
TOPLEVEL_LANG := vhdl
VHDL_SOURCES_libvhdl := ../libvhdl/common/UtilsP.vhd
VHDL_SOURCES := ../libvhdl/syn/*.vhd \
../cryptocores/aes/rtl/vhdl/*.vhd
VHDL_SOURCES_libvhdl := ${EXT}/libvhdl/common/UtilsP.vhd
VHDL_SOURCES := ${EXT}/libvhdl/syn/*.vhd \
${EXT}/cryptocores/aes/rtl/vhdl/*.vhd
SIM_BUILD := work
COMPILE_ARGS := --std=08
SIM_ARGS += \


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