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Add support to use NVC for simulation

master
T. Meissner 12 months ago
parent
commit
86b76548e8
1 changed files with 16 additions and 10 deletions
  1. +16
    -10
      tests/Makefile

+ 16
- 10
tests/Makefile View File

@ -19,18 +19,24 @@ COCOTB_LOG_LEVEL := DEBUG
CUSTOM_COMPILE_DEPS := results
COCOTB_RESULTS_FILE := results/${MODULE}.xml
# Simulator (GHDL) & RTL related
SIM := ghdl
# Simulator & RTL related
SIM ?= ghdl
TOPLEVEL_LANG := vhdl
VHDL_SOURCES_libvhdl := ${EXT}/libvhdl/common/UtilsP.vhd
VHDL_SOURCES := ${EXT}/libvhdl/syn/*.vhd \
VHDL_SOURCES := ${EXT}/libvhdl/syn/* \
${EXT}/cryptocores/aes/rtl/vhdl/*.vhd
SIM_BUILD := work
COMPILE_ARGS := --std=08
SIM_ARGS += \
--wave=results/${MODULE}.ghw \
--psl-report=results/${MODULE}_psl.json \
--vpi-trace=results/${MODULE}_vpi.log
SIM_BUILD := build
ifeq (${SIM}, ghdl)
COMPILE_ARGS := --std=08
SIM_ARGS += \
--wave=results/${MODULE}.ghw \
--psl-report=results/${MODULE}_psl.json \
--vpi-trace=results/${MODULE}_vpi.log
else
EXTRA_ARGS := --std=08
VHDL_LIB_ORDER := libvhdl
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
@ -42,4 +48,4 @@ results:
.PHONY: clean
clean::
rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results
rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results $(SIM_BUILD)

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