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@ -47,7 +47,6 @@ class ParallelTest(AesTest): |
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# Virtual sequence that starts other sequences |
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class TestAllSeq(uvm_sequence): |
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async def body(self): |
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# get the sequencer handle |
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seqr = ConfigDB().get(None, "", "SEQR") |
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@ -59,7 +58,6 @@ class TestAllSeq(uvm_sequence): |
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# Running encryption and decryption sequences in parallel |
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class TestAllParallelSeq(uvm_sequence): |
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async def body(self): |
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seqr = ConfigDB().get(None, "", "SEQR") |
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enc_rand_seq = EncRandSeq("enc_random") |
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@ -71,7 +69,6 @@ class TestAllParallelSeq(uvm_sequence): |
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# Sequence item which holds the stimuli for one operation |
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class AesSeqItem(uvm_sequence_item): |
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def __init__(self, name, mode, key, data): |
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super().__init__(name) |
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self.mode = mode |
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@ -79,7 +76,11 @@ class AesSeqItem(uvm_sequence_item): |
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self.data = data |
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def __eq__(self, other): |
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same = self.mode == other.mode and self.key == other.key and self.data == other.data |
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same = ( |
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self.mode == other.mode |
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and self.key == other.key |
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and self.data == other.data |
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) |
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return same |
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def __str__(self): |
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@ -90,7 +91,6 @@ class AesSeqItem(uvm_sequence_item): |
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# Abstract basis sequence class |
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# set_operands() has to be implemented by class that inherits from this class |
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class BaseSeq(uvm_sequence): |
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async def body(self): |
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self.cr = constraints() |
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for _ in range(20): |
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@ -143,7 +143,6 @@ class Driver(uvm_driver): |
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class Scoreboard(uvm_component): |
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def build_phase(self): |
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self.input_fifo = uvm_tlm_analysis_fifo("input_fifo", self) |
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self.output_fifo = uvm_tlm_analysis_fifo("output_fifo", self) |
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@ -171,12 +170,16 @@ class Scoreboard(uvm_component): |
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else: |
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reference = aes.decrypt(data.buff) |
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if result.buff == reference: |
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self.logger.info(f"PASSED: {Mode(mode).name} {data.hex()} with key " |
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f"{key.hex()} = {result.hex()}") |
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self.logger.info( |
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f"PASSED: {Mode(mode).name} {data.hex()} with key " |
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f"{key.hex()} = {result.hex()}" |
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) |
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else: |
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self.logger.error(f"FAILED: {Mode(mode).name} {data.hex()} with key " |
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f"{key.hex()} = 0x{result.hex()}, " |
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f"expected {reference.hex()}") |
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self.logger.error( |
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f"FAILED: {Mode(mode).name} {data.hex()} with key " |
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f"{key.hex()} = 0x{result.hex()}, " |
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f"expected {reference.hex()}" |
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) |
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self.passed = False |
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def report_phase(self): |
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@ -201,12 +204,10 @@ class Monitor(uvm_component): |
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# Coverage collector and checker |
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class Coverage(uvm_subscriber): |
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def start_of_simulation_phase(self): |
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self.cg = covergroup() |
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try: |
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self.disable_errors = ConfigDB().get( |
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self, "", "DISABLE_COVERAGE_ERRORS") |
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self.disable_errors = ConfigDB().get(self, "", "DISABLE_COVERAGE_ERRORS") |
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except UVMConfigItemNotFound: |
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self.disable_errors = False |
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@ -217,19 +218,17 @@ class Coverage(uvm_subscriber): |
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def report_phase(self): |
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if not self.disable_errors: |
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if self.cg.get_coverage() != 100.0: |
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self.logger.warning( |
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f"Functional coverage incomplete.") |
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self.logger.warning("Functional coverage incomplete.") |
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else: |
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self.logger.info("Covered all operations") |
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with open('results/tb_aes_fcover.txt', 'a', encoding='utf-8') as f: |
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with open("results/tb_aes_fcover.txt", "a", encoding="utf-8") as f: |
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f.write(get_coverage_report(details=True)) |
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vsc.write_coverage_db('results/tb_aes_fcover.xml') |
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vsc.write_coverage_db("results/tb_aes_fcover.xml") |
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# AES test bench environment |
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# Creates instances of components and connects them |
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class AesEnv(uvm_env): |
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def build_phase(self): |
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self.seqr = uvm_sequencer("seqr", self) |
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ConfigDB().set(None, "*", "SEQR", self.seqr) |
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