@ -0,0 +1,4 @@ | |||
v 4 | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/common/UtilsP.vhd" "11fc1f921c5cc44db759fbacca086673488ad2a7" "20240114194831.848": | |||
package utilsp at 1( 0) + 0 on 4; | |||
package body utilsp at 37( 1013) + 0 on 4; |
@ -0,0 +1,36 @@ | |||
v 4 | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/SpiMasterE.vhd" "f09ec5c73ee60bb4bf5affae843aa588b05518bc" "20240114194831.851": | |||
entity spimastere at 1( 0) + 0 on 4; | |||
architecture rtl of spimastere at 36( 1125) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/SpiSlaveE.vhd" "04fba7d5e1ef88072187de5b1329c8a9bc402014" "20240114194831.852": | |||
entity spislavee at 1( 0) + 0 on 4; | |||
architecture rtl of spislavee at 35( 960) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/UartRx.vhd" "52e3a130f357ae260ee22ded47ca4556a03c5a59" "20240114194831.852": | |||
entity uartrx at 21( 1019) + 0 on 4; | |||
architecture rtl of uartrx at 49( 1884) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/UartTx.vhd" "3f8d153c4f2194997742573794afed61480a0f8d" "20240114194831.852": | |||
entity uarttx at 21( 1022) + 0 on 4; | |||
architecture rtl of uarttx at 48( 1813) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/WishBoneCheckerE.vhd" "4f6366f5ceda20267013f682b66267fbe227266b" "20240114194831.852": | |||
entity wishbonecheckere at 1( 0) + 0 on 4; | |||
architecture check of wishbonecheckere at 28( 619) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/WishBoneMasterE.vhd" "c899e200fe03c4944584015fe8f3b270e6ce05db" "20240114194831.853": | |||
entity wishbonemastere at 1( 0) + 0 on 4; | |||
architecture rtl of wishbonemastere at 42( 1216) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/WishBoneP.vhd" "220d27784fed8f2e2cb4dfa665e494225d83af9b" "20240114194831.853": | |||
package wishbonep at 1( 0) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/libvhdl/syn/WishBoneSlaveE.vhd" "6f28f1fee7e34dc09e7666e3f9fe902019547d17" "20240114194831.853": | |||
entity wishboneslavee at 1( 0) + 0 on 4; | |||
architecture rtl of wishboneslavee at 39( 1109) + 0 on 4; | |||
file "/build/pyuvm_tests/" "../ext/cryptocores/aes/rtl/vhdl/aes.vhd" "cabaca485f28b2109d43a1524eeb1987c03f8d83" "20240114194832.428": | |||
entity aes at 22( 1051) + 0 on 17; | |||
architecture rtl of aes at 50( 1873) + 0 on 18; | |||
file "/build/pyuvm_tests/" "../ext/cryptocores/aes/rtl/vhdl/aes_dec.vhd" "4ef897f2b84bd300c603df81b68d374b3b3fa883" "20240114194832.289": | |||
entity aes_dec at 21( 1002) + 0 on 15; | |||
architecture rtl of aes_dec at 48( 1747) + 0 on 16; | |||
file "/build/pyuvm_tests/" "../ext/cryptocores/aes/rtl/vhdl/aes_enc.vhd" "ab0354f24a4814bb0c70a638569ab5c1b15a178e" "20240114194832.153": | |||
entity aes_enc at 21( 1002) + 0 on 13; | |||
architecture rtl of aes_enc at 48( 1748) + 0 on 14; | |||
file "/build/pyuvm_tests/" "../ext/cryptocores/aes/rtl/vhdl/aes_pkg.vhd" "a799bffcc5b16bb191bb36604a1a92299dd20430" "20240114194832.017": | |||
package aes_pkg at 27( 1116) + 0 on 11 body; | |||
package body aes_pkg at 169( 8729) + 0 on 12; |
@ -0,0 +1,7 @@ | |||
<testsuites name="results"> | |||
<testsuite name="all" package="all"> | |||
<property name="random_seed" value="1705261712" /> | |||
<testcase name="AesTest" classname="tb_aes" file="/usr/local/lib/python3.9/dist-packages/pyuvm/extension_classes.py" lineno="27" time="0.4286825656890869" sim_time_ns="6090.000001" ratio_time="14206.316021297982" /> | |||
<testcase name="ParallelTest" classname="tb_aes" file="/usr/local/lib/python3.9/dist-packages/pyuvm/extension_classes.py" lineno="41" time="0.41454362869262695" sim_time_ns="6090.000001" ratio_time="14690.854181516255" /> | |||
</testsuite> | |||
</testsuites> |
@ -0,0 +1,162 @@ | |||
<UCIS xmlns:ucis="http://www.w3.org/2001/XMLSchema-instance" writtenBy="root" writtenTime="2024-01-14T00:00:00" ucisVersion="1.0"> | |||
<sourceFiles fileName="__null__file__" id="1"/> | |||
<sourceFiles fileName="<unknown>" id="2"/> | |||
<sourceFiles fileName="/build/pyuvm_tests/Coverage.py" id="3"/> | |||
<sourceFiles fileName="/build/pyuvm_tests/tb_aes.py" id="4"/> | |||
<historyNodes historyNodeId="0" logicalName="logicalName" physicalName="foo.ucis" kind="HistoryNodeKind.TEST" testStatus="true" simtime="0.0" timeunit="ns" runCwd="." cpuTime="0.0" seed="0" cmd="" args="" compulsory="0" date="2024-01-14T19:48:35" userName="user" cost="0.0" toolCategory="UCIS:simulator" ucisVersion="1.0" vendorId="unknown" vendorTool="unknown" vendorToolVersion="unknown"/> | |||
<instanceCoverages name="cg_inst" key="0"> | |||
<id file="1" line="1" inlineCount="1"/> | |||
<covergroupCoverage> | |||
<cgInstance name="bla" key="0"> | |||
<options/> | |||
<cgId cgName="covergroup" moduleName="covergroup"> | |||
<cginstSourceId file="1" line="1" inlineCount="1"/> | |||
<cgSourceId file="1" line="1" inlineCount="1"/> | |||
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<coverpoint name="enc" key="0"> | |||
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<coverpointBin name="enc" type="bins" key="0"> | |||
<range from="-1" to="-1"> | |||
<contents coverageCount="20"/> | |||
</range> | |||
</coverpointBin> | |||
</coverpoint> | |||
<coverpoint name="dec" key="0"> | |||
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<coverpointBin name="dec" type="bins" key="0"> | |||
<range from="-1" to="-1"> | |||
<contents coverageCount="20"/> | |||
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<range from="-1" to="-1"> | |||
<contents coverageCount="9"/> | |||
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</coverpointBin> | |||
</coverpoint> | |||
<coverpoint name="keyF" key="0"> | |||
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<range from="-1" to="-1"> | |||
<contents coverageCount="7"/> | |||
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</coverpointBin> | |||
</coverpoint> | |||
<cross name="encXkey0" key="0"> | |||
<options/> | |||
<crossExpr>enc</crossExpr> | |||
<crossExpr>key0</crossExpr> | |||
<crossBin name="<enc,key0>" key="0" type="default"> | |||
<index>-1</index> | |||
<contents coverageCount="5"/> | |||
</crossBin> | |||
</cross> | |||
<cross name="encXkeyF" key="0"> | |||
<options/> | |||
<crossExpr>enc</crossExpr> | |||
<crossExpr>keyF</crossExpr> | |||
<crossBin name="<enc,keyF>" key="0" type="default"> | |||
<index>-1</index> | |||
<contents coverageCount="3"/> | |||
</crossBin> | |||
</cross> | |||
<cross name="decXkey0" key="0"> | |||
<options/> | |||
<crossExpr>dec</crossExpr> | |||
<crossExpr>key0</crossExpr> | |||
<crossBin name="<dec,key0>" key="0" type="default"> | |||
<index>-1</index> | |||
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</instanceCoverages> | |||
</UCIS> |
@ -0,0 +1,208 @@ | |||
{ "details" : [ | |||
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{ "directive": "assertion", | |||
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"file": "../ext/cryptocores/aes/rtl/vhdl/aes_dec.vhd", | |||
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{ "directive": "cover", | |||
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"line": 160, | |||
"finished-count": 40, | |||
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"status": "covered"}, | |||
{ "directive": "assertion", | |||
"name": ".aes(rtl).i_aes_dec@aes_dec(rtl).iterg.psl.valid_stable_when_not_accepted_a", | |||
"file": "../ext/cryptocores/aes/rtl/vhdl/aes_dec.vhd", | |||
"line": 161, | |||
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{ "directive": "assertion", | |||
"name": ".aes(rtl).i_aes_dec@aes_dec(rtl).iterg.psl.data_stable_when_not_accepted_a", | |||
"file": "../ext/cryptocores/aes/rtl/vhdl/aes_dec.vhd", | |||
"line": 162, | |||
"finished-count": 0, | |||
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"status": "passed"}], | |||
"summary" : { | |||
"assert": 12, | |||
"assert-failure": 0, | |||
"assert-pass": 12, | |||
"assume": 6, | |||
"assume-failure": 0, | |||
"assume-pass": 6, | |||
"cover": 10, | |||
"cover-failure": 0, | |||
"cover-pass": 10} | |||
} |