tmeissner/cryptocores - cryptocores - goodcleanfun Gitea

cryptography ip-cores in vhdl / verilog

vhdl ghdl osvvm fpga testbenches verilog cryptography

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ci: add GitHub Actions workflow 'test'

3 years ago

ci: update test script

3 years ago

ci: add GitHub Actions workflow 'test'

3 years ago

ci: update test script

3 years ago

ci: add GitHub Actions workflow 'test'

3 years ago

CTR-AES: Fix counter incr & init; add 1st simple testbench * Fix counter init & increase enable to prevent aes_enc PSL assume error * Add CTR-AES testbench, at the moment without data checks

3 years ago

ci: update test script

3 years ago

ci: add GitHub Actions workflow 'test'

3 years ago

#!/usr/bin/env sh

set -e

cd $(dirname "$0")/..

case "$1" in
  sim)
    true
  ;;
  *)
    echo "Unknown test suite '$1'"
    exit 1
  ;;
esac

run_task() {
  echo "::group::Test $1"
  cd "$1"/"$2"/vhdl
  $MAKE "$2"
  cd ../../..
  echo '::endgroup::'
}

for item in aes cbcdes cbcmac_des cbctdes ctraes des tdes; do
  run_task "$item" "$1"
done