cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- DES encryption/decryption testbench
  3. -- tests according to NIST 800-16 special publication
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. -- Revision 1.0 2011/09/17
  19. -- Initial release
  20. -- Revision 1.0.1 2011/09/18
  21. -- tests partial adopted to NIST 800-16 publication
  22. library ieee;
  23. use ieee.std_logic_1164.all;
  24. use ieee.numeric_std.all;
  25. entity tb_des is
  26. end entity tb_des;
  27. architecture rtl of tb_des is
  28. type t_array is array (natural range <>) of std_logic_vector(0 to 63);
  29. signal s_variable_plaintext_known_answers : t_array(0 to 63) :=
  30. (x"95F8A5E5DD31D900", x"DD7F121CA5015619", x"2E8653104F3834EA",
  31. x"4BD388FF6CD81D4F", x"20B9E767B2FB1456", x"55579380D77138EF",
  32. x"6CC5DEFAAF04512F", x"0D9F279BA5D87260", x"D9031B0271BD5A0A",
  33. x"424250B37C3DD951", x"B8061B7ECD9A21E5", x"F15D0F286B65BD28",
  34. x"ADD0CC8D6E5DEBA1", x"E6D5F82752AD63D1", x"ECBFE3BD3F591A5E",
  35. x"F356834379D165CD", x"2B9F982F20037FA9", x"889DE068A16F0BE6",
  36. x"E19E275D846A1298", x"329A8ED523D71AEC", x"E7FCE22557D23C97",
  37. x"12A9F5817FF2D65D", x"A484C3AD38DC9C19", x"FBE00A8A1EF8AD72",
  38. x"750D079407521363", x"64FEED9C724C2FAF", x"F02B263B328E2B60",
  39. x"9D64555A9A10B852", x"D106FF0BED5255D7", x"E1652C6B138C64A5",
  40. x"E428581186EC8F46", x"AEB5F5EDE22D1A36", x"E943D7568AEC0C5C",
  41. x"DF98C8276F54B04B", x"B160E4680F6C696F", x"FA0752B07D9C4AB8",
  42. x"CA3A2B036DBC8502", x"5E0905517BB59BCF", x"814EEB3B91D90726",
  43. x"4D49DB1532919C9F", x"25EB5FC3F8CF0621", x"AB6A20C0620D1C6F",
  44. x"79E90DBC98F92CCA", x"866ECEDD8072BB0E", x"8B54536F2F3E64A8",
  45. x"EA51D3975595B86B", x"CAFFC6AC4542DE31", x"8DD45A2DDF90796C",
  46. x"1029D55E880EC2D0", x"5D86CB23639DBEA9", x"1D1CA853AE7C0C5F",
  47. x"CE332329248F3228", x"8405D1ABE24FB942", x"E643D78090CA4207",
  48. x"48221B9937748A23", x"DD7C0BBD61FAFD54", x"2FBC291A570DB5C4",
  49. x"E07C30D7E4E26E12", x"0953E2258E8E90A1", x"5B711BC4CEEBF2EE",
  50. x"CC083F1E6D9E85F6", x"D2FD8867D50D2DFE", x"06E7EA22CE92708F",
  51. x"166B40B44ABA4BD6");
  52. signal s_clk : std_logic := '0';
  53. signal s_mode : std_logic := '0';
  54. signal s_key : std_logic_vector(0 to 63) := (others => '0');
  55. signal s_datain : std_logic_vector(0 to 63) := (others => '0');
  56. signal s_validin : std_logic := '0';
  57. signal s_dataout : std_logic_vector(0 to 63);
  58. signal s_validout : std_logic;
  59. component des is
  60. port (
  61. clk_i : in std_logic;
  62. mode_i : in std_logic;
  63. key_i : in std_logic_vector(0 TO 63);
  64. data_i : in std_logic_vector(0 TO 63);
  65. valid_i : in std_logic;
  66. data_o : out std_logic_vector(0 TO 63);
  67. valid_o : out std_logic
  68. );
  69. end component des;
  70. begin
  71. s_clk <= not(s_clk) after 10 ns;
  72. teststimuliP : process is
  73. begin
  74. s_mode <= '0';
  75. s_validin <= '0';
  76. s_key <= x"5555555555555555";
  77. s_datain <= x"8000000000000000";
  78. report "# encryption test";
  79. for index in s_variable_plaintext_known_answers'range loop
  80. wait until rising_edge(s_clk);
  81. s_validin <= '1';
  82. if(index /= 0) then
  83. s_datain <= '0' & s_datain(0 to 62);
  84. end if;
  85. end loop;
  86. wait until rising_edge(s_clk);
  87. s_validin <= '0';
  88. wait for 100 ns;
  89. report "# decryption test";
  90. for index in s_variable_plaintext_known_answers'range loop
  91. wait until rising_edge(s_clk);
  92. s_mode <= '1';
  93. s_validin <= '1';
  94. s_datain <= s_variable_plaintext_known_answers(index);
  95. end loop;
  96. wait until rising_edge(s_clk);
  97. s_mode <= '0';
  98. s_validin <= '0';
  99. s_key <= (others => '0');
  100. s_datain <= (others => '0');
  101. wait;
  102. end process teststimuliP;
  103. testcheckerP : process is
  104. variable v_variable_ciphertext_known_answers : std_logic_vector(0 to 63) := x"8000000000000000";
  105. begin
  106. for index in s_variable_plaintext_known_answers'range loop
  107. wait until rising_edge(s_clk) and s_validout = '1';
  108. if(s_dataout /= s_variable_plaintext_known_answers(index)) then
  109. report "encryption error";
  110. end if;
  111. end loop;
  112. for index in s_variable_plaintext_known_answers'range loop
  113. wait until rising_edge(s_clk) and s_validout = '1';
  114. if(s_dataout /= v_variable_ciphertext_known_answers) then
  115. report "decryption error";
  116. end if;
  117. v_variable_ciphertext_known_answers := '0' & v_variable_ciphertext_known_answers(0 to 62);
  118. end loop;
  119. wait;
  120. end process testcheckerP;
  121. i_des : des
  122. port map (
  123. clk_i => s_clk,
  124. mode_i => s_mode,
  125. key_i => s_key,
  126. data_i => s_datain,
  127. valid_i => s_validin,
  128. data_o => s_dataout,
  129. valid_o => s_validout
  130. );
  131. end architecture rtl;