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cryptography ip-cores in vhdl / verilog
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cryptocores/cbcdes/sim/verilog/tb_cbcdes.tcl

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initial commit of verilog simulation environment for verilog cbcdes core
12 years ago
initial commit of cbcdes verilog verification sources
12 years ago
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initial commit of verilog simulation environment for verilog cbcdes core
12 years ago
 
  1. set signals [list]
  2. lappend signals "tb_cbcdes.reset"
  3. lappend signals "tb_cbcdes.clk"
  4. lappend signals "tb_cbcdes.start"
  5. lappend signals "tb_cbcdes.validin"
  6. lappend signals "tb_cbcdes.mode"
  7. lappend signals "tb_cbcdes.key"
  8. lappend signals "tb_cbcdes.iv"
  9. lappend signals "tb_cbcdes.datain"
  10. lappend signals "tb_cbcdes.readyout"
  11. lappend signals "tb_cbcdes.validout"
  12. lappend signals "tb_cbcdes.dataout"
  13. set num_added [ gtkwave::addSignalsFromList $signals ]