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cryptography ip-cores in vhdl / verilog
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Create branch ${ searchTerm }
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cryptocores/tdes/sim/vhdl/tb_tdes.tcl

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moved into seperate vhdl folder
12 years ago
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  1. set signals [list]
  2. lappend signals "top.tb_tdes.s_reset"
  3. lappend signals "top.tb_tdes.s_clk"
  4. lappend signals "top.tb_tdes.s_validin"
  5. lappend signals "top.tb_tdes.s_mode"
  6. lappend signals "top.tb_tdes.s_key1"
  7. lappend signals "top.tb_tdes.s_key2"
  8. lappend signals "top.tb_tdes.s_key3"
  9. lappend signals "top.tb_tdes.s_datain"
  10. lappend signals "top.tb_tdes.s_validout"
  11. lappend signals "top.tb_tdes.s_dataout"
  12. lappend signals "top.tb_tdes.s_ready"
  13. set num_added [ gtkwave::addSignalsFromList $signals ]