cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- TDES encryption/decryption testbench
  3. -- tests according to NIST 800-17 special publication
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. -- Revision 0.1 2011/10/08
  19. -- Initial release
  20. library ieee;
  21. use ieee.std_logic_1164.all;
  22. use ieee.numeric_std.all;
  23. entity tb_tdes is
  24. end entity tb_tdes;
  25. architecture rtl of tb_tdes is
  26. type t_array is array (natural range <>) of std_logic_vector(0 to 63);
  27. constant c_table_test_plain : t_array(0 to 18) :=
  28. (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
  29. x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
  30. x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
  31. x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
  32. x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
  33. x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
  34. x"305532286D6F295A");
  35. signal s_tdes_answers : t_array(0 to 19);
  36. signal s_reset : std_logic := '0';
  37. signal s_clk : std_logic := '0';
  38. signal s_mode : std_logic := '0';
  39. signal s_key1 : std_logic_vector(0 to 63) := (others => '0');
  40. signal s_key2 : std_logic_vector(0 to 63) := (others => '0');
  41. signal s_key3 : std_logic_vector(0 to 63) := (others => '0');
  42. signal s_datain : std_logic_vector(0 to 63) := (others => '0');
  43. signal s_validin : std_logic := '0';
  44. signal s_ready : std_logic := '0';
  45. signal s_dataout : std_logic_vector(0 to 63);
  46. signal s_validout : std_logic := '0';
  47. component tdes is
  48. port (
  49. reset_i : in std_logic;
  50. clk_i : in std_logic;
  51. mode_i : in std_logic;
  52. key1_i : in std_logic_vector(0 to 63);
  53. key2_i : in std_logic_vector(0 TO 63);
  54. key3_i : in std_logic_vector(0 TO 63);
  55. data_i : in std_logic_vector(0 TO 63);
  56. valid_i : in std_logic;
  57. data_o : out std_logic_vector(0 TO 63);
  58. valid_o : out std_logic;
  59. ready_o : out std_logic
  60. );
  61. end component tdes;
  62. begin
  63. s_reset <= '1' after 100 ns;
  64. s_clk <= not(s_clk) after 10 ns;
  65. teststimuliP : process is
  66. begin
  67. s_mode <= '0';
  68. s_validin <= '0';
  69. s_key1 <= (others => '0');
  70. s_key2 <= (others => '0');
  71. s_key3 <= (others => '0');
  72. s_datain <= (others => '0');
  73. -- ENCRYPTION TESTS
  74. -- cbc known answers test
  75. for index in c_table_test_plain'range loop
  76. wait until rising_edge(s_clk) and s_ready = '1';
  77. s_key1 <= x"1111111111111111";
  78. s_key2 <= x"5555555555555555";
  79. s_key3 <= x"9999999999999999";
  80. s_validin <= '1';
  81. s_datain <= c_table_test_plain(index);
  82. wait until rising_edge(s_clk);
  83. s_validin <= '0';
  84. end loop;
  85. wait until rising_edge(s_clk);
  86. s_mode <= '0';
  87. s_validin <= '0';
  88. s_key1 <= (others => '0');
  89. s_key2 <= (others => '0');
  90. s_key3 <= (others => '0');
  91. s_datain <= (others => '0');
  92. wait for 1 us;
  93. -- DECRYPTION TESTS
  94. -- cbc known answer test
  95. for index in c_table_test_plain'range loop
  96. wait until rising_edge(s_clk) and s_ready = '1';
  97. s_key1 <= x"1111111111111111";
  98. s_key2 <= x"5555555555555555";
  99. s_key3 <= x"9999999999999999";
  100. s_mode <= '1';
  101. s_validin <= '1';
  102. s_datain <= s_tdes_answers(index);
  103. wait until rising_edge(s_clk);
  104. s_validin <= '0';
  105. s_mode <= '0';
  106. end loop;
  107. wait until rising_edge(s_clk);
  108. s_mode <= '0';
  109. s_validin <= '0';
  110. s_key1 <= (others => '0');
  111. s_key2 <= (others => '0');
  112. s_key3 <= (others => '0');
  113. s_datain <= (others => '0');
  114. wait;
  115. end process teststimuliP;
  116. testcheckerP : process is
  117. begin
  118. report "# ENCRYPTION TESTS";
  119. for index in c_table_test_plain'range loop
  120. wait until rising_edge(s_clk) and s_validout = '1';
  121. s_tdes_answers(index) <= s_dataout;
  122. end loop;
  123. report "# DECRYPTION TESTS";
  124. report "# tdes known answer test";
  125. for index in c_table_test_plain'range loop
  126. wait until rising_edge(s_clk) and s_validout = '1';
  127. assert (s_dataout = c_table_test_plain(index))
  128. report "decryption error"
  129. severity error;
  130. end loop;
  131. report "# Successfully passed all tests";
  132. wait;
  133. end process testcheckerP;
  134. i_tdes : tdes
  135. port map (
  136. reset_i => s_reset,
  137. clk_i => s_clk,
  138. mode_i => s_mode,
  139. key1_i => s_key1,
  140. key2_i => s_key2,
  141. key3_i => s_key3,
  142. data_i => s_datain,
  143. valid_i => s_validin,
  144. data_o => s_dataout,
  145. valid_o => s_validout,
  146. ready_o => s_ready
  147. );
  148. end architecture rtl;