cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- AES encryption/decryption testbench
  3. -- tests according to NIST special publication
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. -- Revision 0.1 2011/10/22
  19. -- Initial release
  20. library ieee;
  21. use ieee.std_logic_1164.all;
  22. use ieee.numeric_std.all;
  23. entity tb_aes is
  24. end entity tb_aes;
  25. architecture rtl of tb_aes is
  26. signal s_reset : std_logic := '0';
  27. signal s_clk : std_logic := '0';
  28. signal s_mode : std_logic := '0';
  29. signal s_key : std_logic_vector(0 to 127) := (others => '0');
  30. signal s_datain : std_logic_vector(0 to 127) := (others => '0');
  31. signal s_validin : std_logic := '0';
  32. signal s_dataout : std_logic_vector(0 to 127);
  33. signal s_validout : std_logic;
  34. component aes is
  35. port (
  36. reset_i : in std_logic;
  37. clk_i : in std_logic;
  38. mode_i : in std_logic;
  39. key_i : in std_logic_vector(0 TO 127);
  40. data_i : in std_logic_vector(0 TO 127);
  41. valid_i : in std_logic;
  42. data_o : out std_logic_vector(0 TO 127);
  43. valid_o : out std_logic
  44. );
  45. end component aes;
  46. begin
  47. s_clk <= not(s_clk) after 10 ns;
  48. s_reset <= '1' after 100 ns;
  49. i_aes : aes
  50. port map (
  51. reset_i => s_reset,
  52. clk_i => s_clk,
  53. mode_i => s_mode,
  54. key_i => s_key,
  55. data_i => s_datain,
  56. valid_i => s_validin,
  57. data_o => s_dataout,
  58. valid_o => s_validout
  59. );
  60. end architecture rtl;