cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- CBC-DES encryption/decryption testbench
  3. -- tests according to NIST 800-17 special publication
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. entity tb_cbctdes is
  22. end entity tb_cbctdes;
  23. architecture rtl of tb_cbctdes is
  24. type t_array is array (natural range <>) of std_logic_vector(0 to 63);
  25. constant c_table_test_plain : t_array(0 to 18) :=
  26. (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
  27. x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
  28. x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
  29. x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
  30. x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
  31. x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
  32. x"305532286D6F295A");
  33. signal s_tdes_answers : t_array(0 to 19);
  34. signal s_reset : std_logic := '0';
  35. signal s_clk : std_logic := '0';
  36. signal s_mode : std_logic := '0';
  37. signal s_start : std_logic := '0';
  38. signal s_iv : std_logic_vector(0 to 63) := (others => '0');
  39. signal s_key1 : std_logic_vector(0 to 63) := (others => '0');
  40. signal s_key2 : std_logic_vector(0 to 63) := (others => '0');
  41. signal s_key3 : std_logic_vector(0 to 63) := (others => '0');
  42. signal s_datain : std_logic_vector(0 to 63) := (others => '0');
  43. signal s_validin : std_logic := '0';
  44. signal s_ready : std_logic := '0';
  45. signal s_dataout : std_logic_vector(0 to 63);
  46. signal s_validout : std_logic := '0';
  47. component cbctdes is
  48. port (
  49. reset_i : in std_logic;
  50. clk_i : in std_logic;
  51. mode_i : in std_logic;
  52. start_i : in std_logic;
  53. iv_i : in std_logic_vector(0 to 63);
  54. key1_i : in std_logic_vector(0 to 63);
  55. key2_i : in std_logic_vector(0 TO 63);
  56. key3_i : in std_logic_vector(0 TO 63);
  57. data_i : in std_logic_vector(0 TO 63);
  58. valid_i : in std_logic;
  59. data_o : out std_logic_vector(0 TO 63);
  60. valid_o : out std_logic;
  61. ready_o : out std_logic
  62. );
  63. end component cbctdes;
  64. begin
  65. s_reset <= '1' after 100 ns;
  66. s_clk <= not(s_clk) after 10 ns;
  67. teststimuliP : process is
  68. begin
  69. s_start <= '0';
  70. s_mode <= '0';
  71. s_validin <= '0';
  72. s_iv <= (others => '0');
  73. s_key1 <= (others => '0');
  74. s_key2 <= (others => '0');
  75. s_key3 <= (others => '0');
  76. s_datain <= (others => '0');
  77. -- ENCRYPTION TESTS
  78. -- cbc known answers test
  79. for index in c_table_test_plain'range loop
  80. wait until rising_edge(s_clk) and s_ready = '1';
  81. s_key1 <= x"1111111111111111";
  82. s_key2 <= x"5555555555555555";
  83. s_key3 <= x"9999999999999999";
  84. s_validin <= '1';
  85. s_datain <= c_table_test_plain(index);
  86. if(index = 0) then
  87. s_start <= '1';
  88. end if;
  89. wait until rising_edge(s_clk);
  90. s_validin <= '0';
  91. s_start <= '0';
  92. end loop;
  93. wait until rising_edge(s_clk);
  94. s_mode <= '0';
  95. s_start <= '0';
  96. s_validin <= '0';
  97. s_key1 <= (others => '0');
  98. s_key2 <= (others => '0');
  99. s_key3 <= (others => '0');
  100. s_datain <= (others => '0');
  101. wait for 1 us;
  102. -- DECRYPTION TESTS
  103. -- cbc known answer test
  104. for index in c_table_test_plain'range loop
  105. wait until rising_edge(s_clk) and s_ready = '1';
  106. s_key1 <= x"1111111111111111";
  107. s_key2 <= x"5555555555555555";
  108. s_key3 <= x"9999999999999999";
  109. s_mode <= '1';
  110. s_validin <= '1';
  111. s_datain <= s_tdes_answers(index);
  112. if(index = 0) then
  113. s_start <= '1';
  114. end if;
  115. wait until rising_edge(s_clk);
  116. s_start <= '0';
  117. s_validin <= '0';
  118. s_mode <= '0';
  119. end loop;
  120. wait until rising_edge(s_clk);
  121. s_mode <= '0';
  122. s_start <= '0';
  123. s_validin <= '0';
  124. s_key1 <= (others => '0');
  125. s_key2 <= (others => '0');
  126. s_key3 <= (others => '0');
  127. s_datain <= (others => '0');
  128. wait;
  129. end process teststimuliP;
  130. testcheckerP : process is
  131. begin
  132. report "# ENCRYPTION TESTS";
  133. for index in c_table_test_plain'range loop
  134. wait until rising_edge(s_clk) and s_validout = '1';
  135. s_tdes_answers(index) <= s_dataout;
  136. end loop;
  137. report "# DECRYPTION TESTS";
  138. report "# tdes known answer test";
  139. for index in c_table_test_plain'range loop
  140. wait until rising_edge(s_clk) and s_validout = '1';
  141. assert (s_dataout = c_table_test_plain(index))
  142. report "decryption error"
  143. severity error;
  144. end loop;
  145. report "# Successfully passed all tests";
  146. wait;
  147. end process testcheckerP;
  148. i_cbctdes : cbctdes
  149. port map (
  150. reset_i => s_reset,
  151. clk_i => s_clk,
  152. start_i => s_start,
  153. mode_i => s_mode,
  154. iv_i => s_iv,
  155. key1_i => s_key1,
  156. key2_i => s_key2,
  157. key3_i => s_key3,
  158. data_i => s_datain,
  159. valid_i => s_validin,
  160. data_o => s_dataout,
  161. valid_o => s_validout,
  162. ready_o => s_ready
  163. );
  164. end architecture rtl;