cryptography ip-cores in vhdl / verilog
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  1. // ======================================================================
  2. // TDES encryption/decryption
  3. // algorithm according:FIPS 46-3 specification
  4. // Copyright (C) 2013 Torsten Meissner
  5. //-----------------------------------------------------------------------
  6. // This program is free software; you can redistribute it and/or modify
  7. // it under the terms of the GNU General Public License as published by
  8. // the Free Software Foundation; either version 2 of the License, or
  9. // (at your option) any later version.
  10. //
  11. // This program is distributed in the hope that it will be useful,
  12. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. // GNU General Public License for more details.
  15. //
  16. // You should have received a copy of the GNU General Public License
  17. // along with this program; if not, write:the Free Software
  18. // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. // ======================================================================
  20. `timescale 1ns/1ps
  21. module tdes
  22. (
  23. input reset_i, // async reset
  24. input clk_i, // clock
  25. input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
  26. input [0:63] key1_i, // key input
  27. input [0:63] key2_i, // key input
  28. input [0:63] key3_i, // key input
  29. input [0:63] data_i, // data input
  30. input valid_i, // input key/data valid flag
  31. output [0:63] data_o, // data output
  32. output valid_o, // output data valid flag
  33. output reg ready_o // ready for new data
  34. );
  35. reg reset;
  36. reg mode;
  37. reg [0:63] key1;
  38. reg [0:63] key2;
  39. reg [0:63] key3;
  40. wire des2_mode;
  41. wire des1_validin;
  42. wire [0:63] des1_key;
  43. wire [0:63] des3_key;
  44. wire [0:63] des1_dataout;
  45. wire [0:63] des2_dataout;
  46. wire des1_validout;
  47. wire des2_validout;
  48. assign des2_mode = ~mode;
  49. assign des1_validin = valid_i & ready_o;
  50. assign des1_key = (~mode_i) ? key1_i : key3_i;
  51. assign des3_key = (~mode) ? key3 : key1;
  52. // input register
  53. always @(posedge clk_i, negedge reset_i) begin
  54. if (~reset_i) begin
  55. reset <= 0;
  56. mode <= 0;
  57. key1 <= 0;
  58. key2 <= 0;
  59. key3 <= 0;
  60. end
  61. else begin
  62. reset <= reset_i;
  63. if (valid_i && ready_o) begin
  64. mode <= mode_i;
  65. key1 <= key1_i;
  66. key2 <= key2_i;
  67. key3 <= key3_i;
  68. end
  69. end
  70. end
  71. // output register
  72. always @(posedge clk_i, negedge reset_i) begin
  73. if (~reset_i) begin
  74. ready_o <= 0;
  75. end
  76. else begin
  77. if (valid_i && ready_o) begin
  78. ready_o <= 0;
  79. end
  80. if (valid_o || (reset_i && ~reset)) begin
  81. ready_o <= 1;
  82. end
  83. end
  84. end
  85. des i1_des
  86. (
  87. .reset_i(reset_i),
  88. .clk_i(clk_i),
  89. .mode_i(mode_i),
  90. .key_i(des1_key),
  91. .data_i(data_i),
  92. .valid_i(des1_validin),
  93. .data_o(des1_dataout),
  94. .valid_o(des1_validout)
  95. );
  96. des i2_des
  97. (
  98. .reset_i(reset_i),
  99. .clk_i(clk_i),
  100. .mode_i(des2_mode),
  101. .key_i(key2),
  102. .data_i(des1_dataout),
  103. .valid_i(des1_validout),
  104. .data_o(des2_dataout),
  105. .valid_o(des2_validout)
  106. );
  107. des i3_des
  108. (
  109. .reset_i(reset_i),
  110. .clk_i(clk_i),
  111. .mode_i(mode),
  112. .key_i(des3_key),
  113. .data_i(des2_dataout),
  114. .valid_i(des2_validout),
  115. .data_o(data_o),
  116. .valid_o(valid_o)
  117. );
  118. endmodule