cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

628 lines
23 KiB

  1. -- ======================================================================
  2. -- DES encryption/decryption
  3. -- algorithm according to FIPS 46-3 specification
  4. -- Copyright (C) 2007 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. use work.des_pkg.all;
  22. entity des is
  23. generic (
  24. design_type : string := "ITER"
  25. );
  26. port (
  27. reset_i : in std_logic; -- async reset
  28. clk_i : IN std_logic; -- clock
  29. mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  30. key_i : IN std_logic_vector(0 TO 63); -- key input
  31. data_i : IN std_logic_vector(0 TO 63); -- data input
  32. valid_i : IN std_logic; -- input key/data valid
  33. accept_o : out std_logic; -- input data accepted
  34. data_o : OUT std_logic_vector(0 TO 63); -- data output
  35. valid_o : OUT std_logic; -- output data valid flag
  36. accept_i : in std_logic
  37. );
  38. end entity des;
  39. architecture rtl of des is
  40. begin
  41. PipeG : if design_type = "PIPE" generate
  42. begin
  43. crypt : PROCESS (clk_i, reset_i) IS
  44. -- variables for key calculation
  45. VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0');
  46. VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0');
  47. VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0');
  48. VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0');
  49. VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0');
  50. VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0');
  51. VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0');
  52. VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0');
  53. VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0');
  54. VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0');
  55. VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
  56. VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
  57. VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
  58. VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
  59. VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
  60. VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
  61. VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
  62. VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0');
  63. VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0');
  64. VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0');
  65. VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0');
  66. VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0');
  67. VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0');
  68. VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0');
  69. VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0');
  70. VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0');
  71. VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0');
  72. VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
  73. VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
  74. VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
  75. VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
  76. VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
  77. VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
  78. VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
  79. -- key variables
  80. VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0');
  81. VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0');
  82. VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0');
  83. VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0');
  84. VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0');
  85. VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0');
  86. VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0');
  87. VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0');
  88. VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0');
  89. VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
  90. VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
  91. VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
  92. VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
  93. VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
  94. VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
  95. VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
  96. -- variables for left & right data blocks
  97. VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0');
  98. VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0');
  99. VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0');
  100. VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0');
  101. VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0');
  102. VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0');
  103. VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0');
  104. VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0');
  105. VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0');
  106. VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0');
  107. VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
  108. VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
  109. VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
  110. VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
  111. VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
  112. VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
  113. VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
  114. VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0');
  115. VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0');
  116. VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0');
  117. VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0');
  118. VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0');
  119. VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0');
  120. VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0');
  121. VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0');
  122. VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0');
  123. VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0');
  124. VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
  125. VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
  126. VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
  127. VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
  128. VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
  129. VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
  130. VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
  131. -- variables for mode & valid shift registers
  132. VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0');
  133. VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
  134. BEGIN
  135. if(reset_i = '0') then
  136. data_o <= (others => '0');
  137. valid_o <= '0';
  138. elsif rising_edge( clk_i ) THEN
  139. -- shift registers
  140. valid(1 TO 17) := valid(0 TO 16);
  141. valid(0) := valid_i;
  142. mode(1 TO 16) := mode(0 TO 15);
  143. mode(0) := mode_i;
  144. -- output stage
  145. accept_o <= '1';
  146. valid_o <= valid(17);
  147. data_o <= ipn( ( r16 & l16 ) );
  148. -- 16. stage
  149. IF mode(16) = '0' THEN
  150. c16 := c15(1 TO 27) & c15(0);
  151. d16 := d15(1 TO 27) & d15(0);
  152. ELSE
  153. c16 := c15(27) & c15(0 TO 26);
  154. d16 := d15(27) & d15(0 TO 26);
  155. END IF;
  156. key16 := pc2( ( c16 & d16 ) );
  157. l16 := r15;
  158. r16 := l15 xor ( f( r15, key16 ) );
  159. -- 15. stage
  160. IF mode(15) = '0' THEN
  161. c15 := c14(2 TO 27) & c14(0 TO 1);
  162. d15 := d14(2 TO 27) & d14(0 TO 1);
  163. ELSE
  164. c15 := c14(26 TO 27) & c14(0 TO 25);
  165. d15 := d14(26 TO 27) & d14(0 TO 25);
  166. END IF;
  167. key15 := pc2( ( c15 & d15 ) );
  168. l15 := r14;
  169. r15 := l14 xor ( f( r14, key15 ) );
  170. -- 14. stage
  171. IF mode(14) = '0' THEN
  172. c14 := c13(2 TO 27) & c13(0 TO 1);
  173. d14 := d13(2 TO 27) & d13(0 TO 1);
  174. ELSE
  175. c14 := c13(26 TO 27) & c13(0 TO 25);
  176. d14 := d13(26 TO 27) & d13(0 TO 25);
  177. END IF;
  178. key14 := pc2( ( c14 & d14 ) );
  179. l14 := r13;
  180. r14 := l13 xor ( f( r13, key14 ) );
  181. -- 13. stage
  182. IF mode(13) = '0' THEN
  183. c13 := c12(2 TO 27) & c12(0 TO 1);
  184. d13 := d12(2 TO 27) & d12(0 TO 1);
  185. ELSE
  186. c13 := c12(26 TO 27) & c12(0 TO 25);
  187. d13 := d12(26 TO 27) & d12(0 TO 25);
  188. END IF;
  189. key13 := pc2( ( c13 & d13 ) );
  190. l13 := r12;
  191. r13 := l12 xor ( f( r12, key13 ) );
  192. -- 12. stage
  193. IF mode(12) = '0' THEN
  194. c12 := c11(2 TO 27) & c11(0 TO 1);
  195. d12 := d11(2 TO 27) & d11(0 TO 1);
  196. ELSE
  197. c12 := c11(26 TO 27) & c11(0 TO 25);
  198. d12 := d11(26 TO 27) & d11(0 TO 25);
  199. END IF;
  200. key12 := pc2( ( c12 & d12 ) );
  201. l12 := r11;
  202. r12 := l11 xor ( f( r11, key12 ) );
  203. -- 11. stage
  204. IF mode(11) = '0' THEN
  205. c11 := c10(2 TO 27) & c10(0 TO 1);
  206. d11 := d10(2 TO 27) & d10(0 TO 1);
  207. ELSE
  208. c11 := c10(26 TO 27) & c10(0 TO 25);
  209. d11 := d10(26 TO 27) & d10(0 TO 25);
  210. END IF;
  211. key11 := pc2( ( c11 & d11 ) );
  212. l11 := r10;
  213. r11 := l10 xor ( f( r10, key11 ) );
  214. -- 10. stage
  215. IF mode(10) = '0' THEN
  216. c10 := c9(2 TO 27) & c9(0 TO 1);
  217. d10 := d9(2 TO 27) & d9(0 TO 1);
  218. ELSE
  219. c10 := c9(26 TO 27) & c9(0 TO 25);
  220. d10 := d9(26 TO 27) & d9(0 TO 25);
  221. END IF;
  222. key10 := pc2( ( c10 & d10 ) );
  223. l10 := r9;
  224. r10 := l9 xor ( f( r9, key10 ) );
  225. -- 9. stage
  226. IF mode(9) = '0' THEN
  227. c9 := c8(1 TO 27) & c8(0);
  228. d9 := d8(1 TO 27) & d8(0);
  229. ELSE
  230. c9 := c8(27) & c8(0 TO 26);
  231. d9 := d8(27) & d8(0 TO 26);
  232. END IF;
  233. key9 := pc2( ( c9 & d9 ) );
  234. l9 := r8;
  235. r9 := l8 xor ( f( r8, key9 ) );
  236. -- 8. stage
  237. IF mode(8) = '0' THEN
  238. c8 := c7(2 TO 27) & c7(0 TO 1);
  239. d8 := d7(2 TO 27) & d7(0 TO 1);
  240. ELSE
  241. c8 := c7(26 TO 27) & c7(0 TO 25);
  242. d8 := d7(26 TO 27) & d7(0 TO 25);
  243. END IF;
  244. key8 := pc2( ( c8 & d8 ) );
  245. l8 := r7;
  246. r8 := l7 xor ( f( r7, key8 ) );
  247. -- 7. stage
  248. IF mode(7) = '0' THEN
  249. c7 := c6(2 TO 27) & c6(0 TO 1);
  250. d7 := d6(2 TO 27) & d6(0 TO 1);
  251. ELSE
  252. c7 := c6(26 TO 27) & c6(0 TO 25);
  253. d7 := d6(26 TO 27) & d6(0 TO 25);
  254. END IF;
  255. key7 := pc2( ( c7 & d7 ) );
  256. l7 := r6;
  257. r7 := l6 xor ( f( r6, key7 ) );
  258. -- 6. stage
  259. IF mode(6) = '0' THEN
  260. c6 := c5(2 TO 27) & c5(0 TO 1);
  261. d6 := d5(2 TO 27) & d5(0 TO 1);
  262. ELSE
  263. c6 := c5(26 TO 27) & c5(0 TO 25);
  264. d6 := d5(26 TO 27) & d5(0 TO 25);
  265. END IF;
  266. key6 := pc2( ( c6 & d6 ) );
  267. l6 := r5;
  268. r6 := l5 xor ( f( r5, key6 ) );
  269. -- 5. stage
  270. IF mode(5) = '0' THEN
  271. c5 := c4(2 TO 27) & c4(0 TO 1);
  272. d5 := d4(2 TO 27) & d4(0 TO 1);
  273. ELSE
  274. c5 := c4(26 TO 27) & c4(0 TO 25);
  275. d5 := d4(26 TO 27) & d4(0 TO 25);
  276. END IF;
  277. key5 := pc2( ( c5 & d5 ) );
  278. l5 := r4;
  279. r5 := l4 xor ( f( r4, key5 ) );
  280. -- 4. stage
  281. IF mode(4) = '0' THEN
  282. c4 := c3(2 TO 27) & c3(0 TO 1);
  283. d4 := d3(2 TO 27) & d3(0 TO 1);
  284. ELSE
  285. c4 := c3(26 TO 27) & c3(0 TO 25);
  286. d4 := d3(26 TO 27) & d3(0 TO 25);
  287. END IF;
  288. key4 := pc2( ( c4 & d4 ) );
  289. l4 := r3;
  290. r4 := l3 xor ( f( r3, key4 ) );
  291. -- 3. stage
  292. IF mode(3) = '0' THEN
  293. c3 := c2(2 TO 27) & c2(0 TO 1);
  294. d3 := d2(2 TO 27) & d2(0 TO 1);
  295. ELSE
  296. c3 := c2(26 TO 27) & c2(0 TO 25);
  297. d3 := d2(26 TO 27) & d2(0 TO 25);
  298. END IF;
  299. key3 := pc2( ( c3 & d3 ) );
  300. l3 := r2;
  301. r3 := l2 xor ( f( r2, key3 ) );
  302. -- 2. stage
  303. IF mode(2) = '0' THEN
  304. c2 := c1(1 TO 27) & c1(0);
  305. d2 := d1(1 TO 27) & d1(0);
  306. ELSE
  307. c2 := c1(27) & c1(0 TO 26);
  308. d2 := d1(27) & d1(0 TO 26);
  309. END IF;
  310. key2 := pc2( ( c2 & d2 ) );
  311. l2 := r1;
  312. r2 := l1 xor ( f( r1, key2 ) );
  313. -- 1. stage
  314. IF mode(1) = '0' THEN
  315. c1 := c0(1 TO 27) & c0(0);
  316. d1 := d0(1 TO 27) & d0(0);
  317. ELSE
  318. c1 := c0;
  319. d1 := d0;
  320. END IF;
  321. key1 := pc2( ( c1 & d1 ) );
  322. l1 := r0;
  323. r1 := l0 xor ( f( r0, key1 ) );
  324. -- input stage
  325. l0 := ip( data_i )(0 TO 31);
  326. r0 := ip( data_i )(32 TO 63);
  327. c0 := pc1_c( key_i );
  328. d0 := pc1_d( key_i );
  329. END IF;
  330. END PROCESS crypt;
  331. end generate PipeG;
  332. AreaG : if design_type = "ITER" generate
  333. signal s_accept : std_logic;
  334. signal s_valid : std_logic;
  335. signal s_l : std_logic_vector( 0 to 31);
  336. signal s_r : std_logic_vector( 0 to 31);
  337. begin
  338. cryptP : process (clk_i, reset_i) is
  339. variable v_c : std_logic_vector(0 to 27);
  340. variable v_d : std_logic_vector(0 to 27);
  341. variable v_key : std_logic_vector(0 to 47);
  342. variable v_mode : std_logic;
  343. variable v_rnd_cnt : natural;
  344. begin
  345. if(reset_i = '0') then
  346. v_c := (others => '0');
  347. v_d := (others => '0');
  348. v_key := (others => '0');
  349. s_l <= (others => '0');
  350. s_r <= (others => '0');
  351. v_rnd_cnt := 0;
  352. v_mode := '0';
  353. s_accept <= '0';
  354. s_valid <= '0';
  355. elsif rising_edge(clk_i) then
  356. case v_rnd_cnt is
  357. -- input stage
  358. when 0 =>
  359. s_accept <= '1';
  360. s_valid <= '0';
  361. if (valid_i = '1' and s_accept = '1') then
  362. s_accept <= '0';
  363. s_valid <= '0';
  364. s_l <= ip(data_i)(0 to 31);
  365. s_r <= ip(data_i)(32 to 63);
  366. v_c := pc1_c(key_i);
  367. v_d := pc1_d(key_i);
  368. v_mode := mode_i;
  369. v_rnd_cnt := v_rnd_cnt + 1;
  370. end if;
  371. -- stage 1
  372. when 1 =>
  373. if (v_mode = '0') then
  374. v_c := v_c(1 to 27) & v_c(0);
  375. v_d := v_d(1 to 27) & v_d(0);
  376. end if;
  377. v_key := pc2((v_c & v_d));
  378. s_l <= s_r;
  379. s_r <= s_l xor (f(s_r, v_key));
  380. v_rnd_cnt := v_rnd_cnt + 1;
  381. when 2 =>
  382. if (v_mode = '0') then
  383. v_c := v_c(1 to 27) & v_c(0);
  384. v_d := v_d(1 to 27) & v_d(0);
  385. else
  386. v_c := v_c(27) & v_c(0 to 26);
  387. v_d := v_d(27) & v_d(0 to 26);
  388. end if;
  389. v_key := pc2((v_c & v_d));
  390. s_l <= s_r;
  391. s_r <= s_l xor (f(s_r, v_key));
  392. v_rnd_cnt := v_rnd_cnt + 1;
  393. when 3 =>
  394. if (v_mode = '0') then
  395. v_c := v_c(2 to 27) & v_c(0 to 1);
  396. v_d := v_d(2 to 27) & v_d(0 to 1);
  397. else
  398. v_c := v_c(26 to 27) & v_c(0 to 25);
  399. v_d := v_d(26 to 27) & v_d(0 to 25);
  400. end if;
  401. v_key := pc2( ( v_c & v_d ) );
  402. s_l <= s_r;
  403. s_r <= s_l xor ( f( s_r, v_key ) );
  404. v_rnd_cnt := v_rnd_cnt + 1;
  405. when 4 =>
  406. if (v_mode = '0') then
  407. v_c := v_c(2 to 27) & v_c(0 to 1);
  408. v_d := v_d(2 to 27) & v_d(0 to 1);
  409. else
  410. v_c := v_c(26 to 27) & v_c(0 to 25);
  411. v_d := v_d(26 to 27) & v_d(0 to 25);
  412. end if;
  413. v_key := pc2( ( v_c & v_d ) );
  414. s_l <= s_r;
  415. s_r <= s_l xor ( f( s_r, v_key ) );
  416. v_rnd_cnt := v_rnd_cnt + 1;
  417. when 5 =>
  418. if (v_mode = '0') then
  419. v_c := v_c(2 to 27) & v_c(0 to 1);
  420. v_d := v_d(2 to 27) & v_d(0 to 1);
  421. else
  422. v_c := v_c(26 to 27) & v_c(0 to 25);
  423. v_d := v_d(26 to 27) & v_d(0 to 25);
  424. end if;
  425. v_key := pc2( ( v_c & v_d ) );
  426. s_l <= s_r;
  427. s_r <= s_l xor ( f( s_r, v_key ) );
  428. v_rnd_cnt := v_rnd_cnt + 1;
  429. when 6 =>
  430. if (v_mode = '0') then
  431. v_c := v_c(2 to 27) & v_c(0 to 1);
  432. v_d := v_d(2 to 27) & v_d(0 to 1);
  433. else
  434. v_c := v_c(26 to 27) & v_c(0 to 25);
  435. v_d := v_d(26 to 27) & v_d(0 to 25);
  436. end if;
  437. v_key := pc2( ( v_c & v_d ) );
  438. s_l <= s_r;
  439. s_r <= s_l xor ( f( s_r, v_key ) );
  440. v_rnd_cnt := v_rnd_cnt + 1;
  441. when 7 =>
  442. if (v_mode = '0') then
  443. v_c := v_c(2 to 27) & v_c(0 to 1);
  444. v_d := v_d(2 to 27) & v_d(0 to 1);
  445. else
  446. v_c := v_c(26 to 27) & v_c(0 to 25);
  447. v_d := v_d(26 to 27) & v_d(0 to 25);
  448. end if;
  449. v_key := pc2( ( v_c & v_d ) );
  450. s_l <= s_r;
  451. s_r <= s_l xor ( f( s_r, v_key ) );
  452. v_rnd_cnt := v_rnd_cnt + 1;
  453. when 8 =>
  454. if (v_mode = '0') then
  455. v_c := v_c(2 to 27) & v_c(0 to 1);
  456. v_d := v_d(2 to 27) & v_d(0 to 1);
  457. else
  458. v_c := v_c(26 to 27) & v_c(0 to 25);
  459. v_d := v_d(26 to 27) & v_d(0 to 25);
  460. end if;
  461. v_key := pc2( ( v_c & v_d ) );
  462. s_l <= s_r;
  463. s_r <= s_l xor ( f( s_r, v_key ) );
  464. v_rnd_cnt := v_rnd_cnt + 1;
  465. when 9 =>
  466. if (v_mode = '0') then
  467. v_c := v_c(1 to 27) & v_c(0);
  468. v_d := v_d(1 to 27) & v_d(0);
  469. else
  470. v_c := v_c(27) & v_c(0 to 26);
  471. v_d := v_d(27) & v_d(0 to 26);
  472. end if;
  473. v_key := pc2( ( v_c & v_d ) );
  474. s_l <= s_r;
  475. s_r <= s_l xor ( f( s_r, v_key ) );
  476. v_rnd_cnt := v_rnd_cnt + 1;
  477. when 10 =>
  478. if (v_mode = '0') then
  479. v_c := v_c(2 to 27) & v_c(0 to 1);
  480. v_d := v_d(2 to 27) & v_d(0 to 1);
  481. else
  482. v_c := v_c(26 to 27) & v_c(0 to 25);
  483. v_d := v_d(26 to 27) & v_d(0 to 25);
  484. end if;
  485. v_key := pc2( ( v_c & v_d ) );
  486. s_l <= s_r;
  487. s_r <= s_l xor ( f( s_r, v_key ) );
  488. v_rnd_cnt := v_rnd_cnt + 1;
  489. when 11 =>
  490. -- 11. stage
  491. if (v_mode = '0') then
  492. v_c := v_c(2 to 27) & v_c(0 to 1);
  493. v_d := v_d(2 to 27) & v_d(0 to 1);
  494. else
  495. v_c := v_c(26 to 27) & v_c(0 to 25);
  496. v_d := v_d(26 to 27) & v_d(0 to 25);
  497. end if;
  498. v_key := pc2( ( v_c & v_d ) );
  499. s_l <= s_r;
  500. s_r <= s_l xor ( f( s_r, v_key ) );
  501. v_rnd_cnt := v_rnd_cnt + 1;
  502. when 12 =>
  503. if (v_mode = '0') then
  504. v_c := v_c(2 to 27) & v_c(0 to 1);
  505. v_d := v_d(2 to 27) & v_d(0 to 1);
  506. else
  507. v_c := v_c(26 to 27) & v_c(0 to 25);
  508. v_d := v_d(26 to 27) & v_d(0 to 25);
  509. end if;
  510. v_key := pc2( ( v_c & v_d ) );
  511. s_l <= s_r;
  512. s_r <= s_l xor ( f( s_r, v_key ) );
  513. v_rnd_cnt := v_rnd_cnt + 1;
  514. when 13 =>
  515. if (v_mode = '0') then
  516. v_c := v_c(2 to 27) & v_c(0 to 1);
  517. v_d := v_d(2 to 27) & v_d(0 to 1);
  518. else
  519. v_c := v_c(26 to 27) & v_c(0 to 25);
  520. v_d := v_d(26 to 27) & v_d(0 to 25);
  521. end if;
  522. v_key := pc2( ( v_c & v_d ) );
  523. s_l <= s_r;
  524. s_r <= s_l xor ( f( s_r, v_key ) );
  525. v_rnd_cnt := v_rnd_cnt + 1;
  526. when 14 =>
  527. if (v_mode = '0') then
  528. v_c := v_c(2 to 27) & v_c(0 to 1);
  529. v_d := v_d(2 to 27) & v_d(0 to 1);
  530. else
  531. v_c := v_c(26 to 27) & v_c(0 to 25);
  532. v_d := v_d(26 to 27) & v_d(0 to 25);
  533. end if;
  534. v_key := pc2( ( v_c & v_d ) );
  535. s_l <= s_r;
  536. s_r <= s_l xor ( f( s_r, v_key ) );
  537. v_rnd_cnt := v_rnd_cnt + 1;
  538. when 15 =>
  539. if (v_mode = '0') then
  540. v_c := v_c(2 to 27) & v_c(0 to 1);
  541. v_d := v_d(2 to 27) & v_d(0 to 1);
  542. else
  543. v_c := v_c(26 to 27) & v_c(0 to 25);
  544. v_d := v_d(26 to 27) & v_d(0 to 25);
  545. end if;
  546. v_key := pc2( ( v_c & v_d ) );
  547. s_l <= s_r;
  548. s_r <= s_l xor ( f( s_r, v_key ) );
  549. v_rnd_cnt := v_rnd_cnt + 1;
  550. when 16 =>
  551. if (v_mode = '0') then
  552. v_c := v_c(1 to 27) & v_c(0);
  553. v_d := v_d(1 to 27) & v_d(0);
  554. else
  555. v_c := v_c(27) & v_c(0 to 26);
  556. v_d := v_d(27) & v_d(0 to 26);
  557. end if;
  558. v_key := pc2( ( v_c & v_d ) );
  559. s_l <= s_r;
  560. s_r <= s_l xor ( f( s_r, v_key ) );
  561. v_rnd_cnt := v_rnd_cnt + 1;
  562. when 17 =>
  563. s_valid <= '1';
  564. if (s_valid = '1') then
  565. if(accept_i = '1') then
  566. s_valid <= '0';
  567. v_rnd_cnt := 0;
  568. end if;
  569. end if;
  570. when others =>
  571. null;
  572. end case;
  573. end if;
  574. end process cryptP;
  575. valid_o <= s_valid;
  576. accept_o <= s_accept;
  577. data_o <= ipn(s_r & s_l) when s_valid = '1' else (others => '0');
  578. end generate AreaG;
  579. END ARCHITECTURE rtl;