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cryptography ip-cores in vhdl / verilog
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cryptocores/cbctdes/sim/tb_cbctdes.tcl

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integrated tcl-file into gtkwave starting parameters
13 years ago
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  1. set signals [list]
  2. lappend signals "top.tb_cbctdes.s_reset"
  3. lappend signals "top.tb_cbctdes.s_clk"
  4. lappend signals "top.tb_cbctdes.s_validin"
  5. lappend signals "top.tb_cbctdes.s_start"
  6. lappend signals "top.tb_cbctdes.s_mode"
  7. lappend signals "top.tb_cbctdes.s_key"
  8. lappend signals "top.tb_cbctdes.s_iv"
  9. lappend signals "top.tb_cbctdes.s_datain"
  10. lappend signals "top.tb_cbctdes.s_validout"
  11. lappend signals "top.tb_cbctdes.s_dataout"
  12. lappend signals "top.tb_cbctdes.s_ready"
  13. set num_added [ gtkwave::addSignalsFromList $signals ]