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cryptocores
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cryptography ip-cores in vhdl / verilog
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cryptocores/des/sim/verilog/tb_des.tcl

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new verilog testbench, makefile & tcl-file
13 years ago
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  1. set signals [list]
  2. lappend signals "tb_des.reset"
  3. lappend signals "tb_des.clk"
  4. lappend signals "tb_des.validin"
  5. lappend signals "tb_des.mode"
  6. lappend signals "tb_des.key"
  7. lappend signals "tb_des.datain"
  8. lappend signals "tb_des.validout"
  9. lappend signals "tb_des.dataout"
  10. set num_added [ gtkwave::addSignalsFromList $signals ]