cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- CBC-DES encryption/decryption
  3. -- algorithm according to FIPS 46-3 specification
  4. -- Copyright (C) 2007 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. -- Revision 0.1 2011/09/23
  19. -- Initial release, incomplete and may contain bugs
  20. -- Revision 0.2 2011/10/06
  21. -- corrected some bugs which were found while testing cbc ability
  22. library ieee;
  23. use ieee.std_logic_1164.all;
  24. use ieee.numeric_std.all;
  25. use work.des_pkg.all;
  26. entity cbcdes is
  27. port (
  28. reset_i : in std_logic; -- low active async reset
  29. clk_i : in std_logic; -- clock
  30. start_i : in std_logic; -- start cbc
  31. mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  32. key_i : in std_logic_vector(0 TO 63); -- key input
  33. iv_i : in std_logic_vector(0 to 63); -- iv input
  34. data_i : in std_logic_vector(0 TO 63); -- data input
  35. valid_i : in std_logic; -- input key/data valid flag
  36. ready_o : out std_logic; -- ready to encrypt/decrypt
  37. data_o : out std_logic_vector(0 TO 63); -- data output
  38. valid_o : out std_logic -- output data valid flag
  39. );
  40. end entity cbcdes;
  41. architecture rtl of cbcdes is
  42. component des is
  43. port (
  44. reset_i : in std_logic;
  45. clk_i : IN std_logic; -- clock
  46. mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  47. key_i : IN std_logic_vector(0 TO 63); -- key input
  48. data_i : IN std_logic_vector(0 TO 63); -- data input
  49. valid_i : IN std_logic; -- input key/data valid flag
  50. data_o : OUT std_logic_vector(0 TO 63); -- data output
  51. valid_o : OUT std_logic -- output data valid flag
  52. );
  53. end component des;
  54. signal s_mode : std_logic;
  55. signal s_des_mode : std_logic;
  56. signal s_start : std_logic;
  57. signal s_key : std_logic_vector(0 to 63);
  58. signal s_des_key : std_logic_vector(0 to 63);
  59. signal s_iv : std_logic_vector(0 to 63);
  60. signal s_datain : std_logic_vector(0 to 63);
  61. signal s_datain_d : std_logic_vector(0 to 63);
  62. signal s_des_datain : std_logic_vector(0 to 63);
  63. signal s_validin : std_logic;
  64. signal s_des_dataout : std_logic_vector(0 to 63);
  65. signal s_dataout : std_logic_vector(0 to 63);
  66. signal s_validout : std_logic;
  67. signal s_ready : std_logic;
  68. signal s_reset : std_logic;
  69. begin
  70. s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
  71. s_dataout xor data_i when s_mode = '0' and start_i = '0' else
  72. data_i;
  73. data_o <= s_iv xor s_des_dataout when s_mode = '1' and s_start = '1' else
  74. s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
  75. s_des_dataout;
  76. s_des_key <= key_i when start_i = '1' else s_key;
  77. s_des_mode <= mode_i when start_i = '1' else s_mode;
  78. ready_o <= s_ready;
  79. s_validin <= valid_i and s_ready;
  80. valid_o <= s_validout;
  81. inputregister : process(clk_i, reset_i) is
  82. begin
  83. if(reset_i = '0') then
  84. s_reset <= '0';
  85. s_mode <= '0';
  86. s_start <= '0';
  87. s_key <= (others => '0');
  88. s_iv <= (others => '0');
  89. s_datain <= (others => '0');
  90. s_datain_d <= (others => '0');
  91. elsif(rising_edge(clk_i)) then
  92. s_reset <= reset_i;
  93. if(valid_i = '1' and s_ready = '1') then
  94. s_start <= start_i;
  95. s_datain <= data_i;
  96. s_datain_d <= s_datain;
  97. end if;
  98. if(valid_i = '1' and s_ready = '1' and start_i = '1') then
  99. s_mode <= mode_i;
  100. s_key <= key_i;
  101. s_iv <= iv_i;
  102. end if;
  103. end if;
  104. end process inputregister;
  105. outputregister : process(clk_i, reset_i) is
  106. begin
  107. if(reset_i = '0') then
  108. s_ready <= '0';
  109. s_dataout <= (others => '0');
  110. elsif(rising_edge(clk_i)) then
  111. if(valid_i = '1' and s_ready = '1') then
  112. s_ready <= '0';
  113. end if;
  114. if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
  115. s_ready <= '1';
  116. s_dataout <= s_des_dataout;
  117. end if;
  118. end if;
  119. end process outputregister;
  120. i_des : des
  121. port map (
  122. reset_i => s_reset,
  123. clk_i => clk_i,
  124. mode_i => s_des_mode,
  125. key_i => s_des_key,
  126. data_i => s_des_datain,
  127. valid_i => s_validin,
  128. data_o => s_des_dataout,
  129. valid_o => s_validout
  130. );
  131. end architecture rtl;