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@ -22,6 +22,9 @@ library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use ieee.numeric_std.all; |
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library osvvm; |
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use osvvm.RandomPkg.all; |
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use std.env.all; |
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use std.env.all; |
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use work.aes_pkg.all; |
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use work.aes_pkg.all; |
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@ -52,6 +55,27 @@ architecture rtl of tb_aes is |
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signal s_validout_dec : std_logic; |
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signal s_validout_dec : std_logic; |
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signal s_acceptin_dec : std_logic := '0'; |
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signal s_acceptin_dec : std_logic := '0'; |
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procedure cryptData(datain : in std_logic_vector(0 to 127); |
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key : in std_logic_vector(0 to 127); |
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mode : in boolean; |
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dataout : out std_logic_vector(0 to 127); |
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len : in integer) is |
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begin |
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report "VHPIDIRECT cryptData" severity failure; |
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end procedure; |
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attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData"; |
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function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is |
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variable v_data : std_logic_vector(0 to 127); |
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begin |
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for i in 0 to 15 loop |
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for y in 0 to 7 loop |
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v_data((i*8)+y) := datain((i*8)+7-y); |
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end loop; |
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end loop; |
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return v_data; |
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end function; |
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begin |
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begin |
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@ -89,37 +113,52 @@ begin |
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process is |
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process is |
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variable v_key : std_logic_vector(0 to 127); |
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variable v_datain : std_logic_vector(0 to 127); |
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variable v_dataout : std_logic_vector(0 to 127); |
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variable v_random : RandomPType; |
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begin |
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begin |
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v_random.InitSeed(v_random'instance_name); |
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wait until s_reset = '1'; |
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wait until s_reset = '1'; |
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-- ENCRYPTION TEST |
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-- ENCRYPTION TESTs |
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report "Test encryption"; |
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report "Test encryption"; |
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wait until rising_edge(s_clk); |
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s_validin_enc <= '1'; |
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s_key <= x"2b7e151628aed2a6abf7158809cf4f3c"; |
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s_datain <= x"3243f6a8885a308d313198a2e0370734"; |
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wait until s_acceptout_enc = '1' and rising_edge(s_clk); |
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s_validin_enc <= '0'; |
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wait until s_validout_enc = '1' and rising_edge(s_clk); |
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s_acceptin_enc <= '1'; |
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assert s_dataout_enc = x"3925841D02DC09FBDC118597196A0B32" |
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report "Encryption error" |
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severity failure; |
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s_datain <= s_dataout_enc; |
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wait until rising_edge(s_clk); |
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s_acceptin_enc <= '0'; |
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-- DECRYPTION TEST |
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for i in 0 to 63 loop |
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wait until rising_edge(s_clk); |
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s_validin_enc <= '1'; |
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v_key := v_random.RandSlv(128); |
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v_datain := v_random.RandSlv(128); |
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s_key <= v_key; |
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s_datain <= v_datain; |
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cryptData(swap(v_datain), swap(v_key), true, v_dataout, 128); |
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wait until s_acceptout_enc = '1' and rising_edge(s_clk); |
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s_validin_enc <= '0'; |
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wait until s_validout_enc = '1' and rising_edge(s_clk); |
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s_acceptin_enc <= '1'; |
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assert s_dataout_enc = swap(v_dataout) |
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report "Encryption error" |
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severity failure; |
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wait until rising_edge(s_clk); |
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s_acceptin_enc <= '0'; |
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end loop; |
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-- DECRYPTION TESTs |
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report "Test decryption"; |
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report "Test decryption"; |
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wait until rising_edge(s_clk); |
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s_validin_dec <= '1'; |
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wait until s_acceptout_dec = '1' and rising_edge(s_clk); |
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s_validin_dec <= '0'; |
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wait until s_validout_dec = '1' and rising_edge(s_clk); |
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s_acceptin_dec <= '1'; |
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assert s_dataout_dec = x"3243f6a8885a308d313198a2e0370734" |
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report "Decryption error" |
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severity failure; |
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wait until rising_edge(s_clk); |
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s_acceptin_dec <= '0'; |
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for i in 0 to 63 loop |
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wait until rising_edge(s_clk); |
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s_validin_dec <= '1'; |
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v_key := x"2b7e151628aed2a6abf7158809cf4f3c"; |
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v_datain := x"3925841D02DC09FBDC118597196A0B32"; |
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s_key <= v_key; |
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s_datain <= v_datain; |
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wait until s_acceptout_dec = '1' and rising_edge(s_clk); |
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s_validin_dec <= '0'; |
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wait until s_validout_dec = '1' and rising_edge(s_clk); |
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s_acceptin_dec <= '1'; |
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assert s_dataout_dec = x"3243f6a8885a308d313198a2e0370734" |
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report "Decryption error" |
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severity failure; |
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wait until rising_edge(s_clk); |
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s_acceptin_dec <= '0'; |
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end loop; |
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wait for 100 ns; |
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wait for 100 ns; |
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report "Tests successful"; |
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report "Tests successful"; |
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finish(0); |
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finish(0); |
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