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dependency files now moved into 2 variables SRC_FILES & SIM_FILES

master
T. Meissner 11 years ago
parent
commit
10bcd87d1b
1 changed files with 5 additions and 1 deletions
  1. +5
    -1
      des/sim/verilog/makefile

+ 5
- 1
des/sim/verilog/makefile View File

@ -19,12 +19,16 @@
# ======================================================================
SRC_FILES = ../../rtl/verilog/*.v tb_des.v
SIM_FILES = data_input.txt key_input.txt data_output.txt
all : sim wave
sim : tb_des.vcd
tb_des.vcd : ../../rtl/verilog/*.v tb_des.v
tb_des.vcd : $(SRC_FILES) $(SIM_FILES)
iverilog -Wall -s tb_des -o tb_des tb_des.v ../../rtl/verilog/des.v
vvp tb_des


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