Minor refactoring & bugfixing

* Set VHDL standard to VHDL 2008
* Replace rcon() functuion by simple array constant
* Correct loop range in addroundkey() function

aes/rtl/vhdl/aes.vhd

@@ -28,6 +28,9 @@ use work.aes_pkg.all;
 
 
 entity aes is
+  generic (
+    design_type : string := "ITER"
+  );
   port (
     reset_i     : in  std_logic;                   -- async reset
     clk_i       : in  std_logic;                   -- clock
@@ -47,47 +50,15 @@ end entity aes;
 architecture rtl of aes is
 
 
-  signal s_fsm_state : t_rounds;
-  signal s_aes_state : t_datatable2d;
-  signal s_accept : std_logic;
-  signal s_key_sched_done : boolean;
-
-
 begin
 
 
-  KeySchedP : process (reset_i, clk_i) is
-  begin
+  PipeG : if design_type = "PIPE" generate
 
-  end process KeySchedP;
+  begin
 
 
-  AesIter: process (reset_i, clk_i) is
-    variable v_mode      : std_logic;
-    variable v_round_cnt : t_rounds;
-    variable v_key       : t_key;
-  begin
-    if(reset_i = '0') then
-      s_accept    <= '1';
-      data_o      <= (others => '0');
-      valid_o     <= '0';
-      v_mode      := '0';
-      v_key       := (others => (others => '0'));
-      v_round_cnt := t_rounds'low;
-    elsif rising_edge(clk_i) then
-      FsmC : case s_fsm_state is
-
-        when 0 =>
-          if(s_accept = '1' and valid_i = '1') then
-            v_mode := mode_i;
-          end if;
-
-      end case FsmC;
-    end if;
-  end process AesIter;
-
-
-  accept_o <= s_accept;
+  end generate PipeG;
 
 
 end architecture rtl;

aes/rtl/vhdl/aes_pkg.vhd

@@ -48,6 +48,8 @@ package aes_pkg is
   type t_stable2d is array (0 to 15) of t_stable1d;
 
   type t_key is array (0 to 3) of std_logic_vector(31 downto 0);
+  
+  type t_rcon is array (0 to 9) of t_datatable1d;
 
   constant c_sbox : t_stable2d := (
     -- 0     1      2      3      4      5      6      7      8      9      A      B      C      D      E      F
@@ -87,6 +89,18 @@ package aes_pkg is
     (x"a0", x"e0", x"3b", x"4d", x"ae", x"2a", x"f5", x"b0", x"c8", x"eb", x"bb", x"3c", x"83", x"53", x"99", x"61"), -- E
     (x"17", x"2b", x"04", x"7e", x"ba", x"77", x"d6", x"26", x"e1", x"69", x"14", x"63", x"55", x"21", x"0c", x"7d"));-- F
 
+  constant c_rcon : t_rcon := (
+    (x"01", x"00", x"00", x"00"),
+    (x"02", x"00", x"00", x"00"),
+    (x"04", x"00", x"00", x"00"),
+    (x"08", x"00", x"00", x"00"),
+    (x"10", x"00", x"00", x"00"),
+    (x"20", x"00", x"00", x"00"),
+    (x"40", x"00", x"00", x"00"),
+    (x"80", x"00", x"00", x"00"),
+    (x"1B", x"00", x"00", x"00"),
+    (x"36", x"00", x"00", x"00"));
+
 
   function bytesub    (input : std_logic_vector(7 downto 0)) return std_logic_vector;
   function invbytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector;
@@ -95,6 +109,7 @@ package aes_pkg is
   function invshiftrow (input : t_datatable2d) return t_datatable2d;
 
   function mixcolumns (input : t_datatable2d; column : natural) return t_datatable2d;
+  function invmixcolumns (input : t_datatable2d; column : natural) return t_datatable2d;
 
   function sortdata (input : std_logic_vector(127 downto 0)) return t_datatable2d;
 
@@ -106,8 +121,6 @@ package aes_pkg is
 
   function rotword (input : in t_datatable1d) return t_datatable1d;
 
-  function rcon (round : in t_rounds) return t_datatable1d;
-
 
 end package aes_pkg;
 
@@ -236,7 +249,7 @@ package body aes_pkg is
     variable v_data : t_datatable2d;
     variable v_key  : t_datatable1d;
   begin
-    for i in 0 to 2 loop
+    for i in 0 to 3 loop
       v_key := (key(i)(7 downto 0), key(i)(15 downto 8), key(i)(23 downto 16), key(i)(31 downto 24));
       for j in 0 to 3 loop
         v_data(i)(j) := input(i)(j) xor v_key(j);
@@ -262,12 +275,4 @@ package body aes_pkg is
   end function rotword;
 
 
-  function rcon (round : in t_rounds) return t_datatable1d is
-    variable v_data : std_logic_vector(15 downto 0);
-  begin
-    v_data := std_logic_vector(to_unsigned(2**(round-1), 15));
-    return(v_data(7 downto 0), x"00", x"00", x"00");
-  end function rcon;
-
-
 end package body aes_pkg;

aes/sim/vhdl/makefile

@@ -24,8 +24,8 @@ all : sim wave
 sim : tb_aes.ghw
 
 compile : ../../rtl/vhdl/*.vhd tb_aes.vhd
-	ghdl -a ../../rtl/vhdl/aes_pkg.vhd ../../rtl/vhdl/aes.vhd tb_aes.vhd
-	ghdl -e tb_aes
+	ghdl -a --std=08 ../../rtl/vhdl/aes_pkg.vhd ../../rtl/vhdl/aes.vhd tb_aes.vhd
+	ghdl -e --std=08 tb_aes
 
 tb_aes.ghw : compile
 	ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us