further converting of vhdl into verilog code

des/rtl/verilog/des.v

@@ -235,7 +235,7 @@ module des
     end
     else begin
       // output stage
-      data_o  <= ipn({r16, l16});
+      data_o = ipn({r16, l16});
       // 16. stage
       if (mode[16] == 1'b0) begin
         c16 = {c15[1:27], c15[0]};
@@ -296,102 +296,102 @@ module des
       key12 = pc2({c12, d12});
       l12   = r11;
       r12   = l11 ^ (f(r11, key12));
-      /*// 11. stage
+      // 11. stage
       if (mode[11] == 1'b0) begin
-        c11 = c10(2:27], c10(0:1];
-        d11 = d10(2:27], d10(0:1];
+        c11 = {c10[2:27], c10[0:1]};
+        d11 = {d10[2:27], d10[0:1]};
       end
       else begin
-        c11 = c10(26:27], c10(0:25];
-        d11 = d10(26:27], d10(0:25];
+        c11 = {c10[26:27], c10[0:25]};
+        d11 = {d10[26:27], d10[0:25]};
       end
-      key11 = pc2( ( c11, d11 ) ];
-      l11 = r10;
-      r11 = l10 ^ ( f( r10, key11 ) ];
+      key11 = pc2({c11, d11});
+      l11   = r10;
+      r11   = l10 ^ (f(r10, key11));
       // 10. stage
       if (mode[10] == 1'b0) begin
-        c10 = c9(2:27], c9(0:1];
-        d10 = d9(2:27], d9(0:1];
+        c10 = {c9[2:27], c9[0:1]};
+        d10 = {d9[2:27], d9[0:1]};
       end
       else begin
-        c10 = c9(26:27], c9(0:25];
-        d10 = d9(26:27], d9(0:25];
+        c10 = {c9[26:27], c9[0:25]};
+        d10 = {d9[26:27], d9[0:25]};
       end
-      key10 = pc2( ( c10, d10 ) ];
-      l10 = r9;
-      r10 = l9 ^ ( f( r9, key10 ) ];
+      key10 = pc2({c10, d10});
+      l10   = r9;
+      r10   = l9 ^ (f(r9, key10));
       // 9. stage
       if (mode[9] == 1'b0) begin
-        c9 = c8(1:27], c8(0];
-        d9 = d8(1:27], d8(0];
+        c9 = {c8[1:27], c8[0]};
+        d9 = {d8[1:27], d8[0]};
       end
       else begin
-        c9 = c8(27], c8(0:26];
-        d9 = d8(27], d8(0:26];
+        c9 = {c8[27], c8[0:26]};
+        d9 = {d8[27], d8[0:26]};
       end
-      key9 = pc2( ( c9, d9 ) ];
-      l9 = r8;
-      r9 = l8 ^ ( f( r8, key9 ) ];
+      key9 = pc2({c9, d9});
+      l9   = r8;
+      r9   = l8 ^ (f(r8, key9));
       // 8. stage
       if (mode[8] == 1'b0) begin
-        c8 = c7(2:27], c7(0:1];
-        d8 = d7(2:27], d7(0:1];
+        c8 = {c7[2:27], c7[0:1]};
+        d8 = {d7[2:27], d7[0:1]};
       end
       else begin
-        c8 = c7(26:27], c7(0:25];
-        d8 = d7(26:27], d7(0:25];
+        c8 = {c7[26:27], c7[0:25]};
+        d8 = {d7[26:27], d7[0:25]};
       end
-      key8 = pc2( ( c8, d8 ) ];
-      l8 = r7;
-      r8 = l7 ^ ( f( r7, key8 ) ];
+      key8 = pc2({c8, d8});
+      l8   = r7;
+      r8   = l7 ^ (f(r7, key8));
       // 7. stage
       if (mode[7] == 1'b0) begin
-        c7 = c6(2:27], c6(0:1];
-        d7 = d6(2:27], d6(0:1];
+        c7 = {c6[2:27], c6[0:1]};
+        d7 = {d6[2:27], d6[0:1]};
       end
       else begin
-        c7 = c6(26:27], c6(0:25];
-        d7 = d6(26:27], d6(0:25];
+        c7 = {c6[26:27], c6[0:25]};
+        d7 = {d6[26:27], d6[0:25]};
       end
-      key7 = pc2( ( c7, d7 ) ];
-      l7 = r6;
-      r7 = l6 ^ ( f( r6, key7 ) ];
+      key7 = pc2({c7, d7});
+      l7   = r6;
+      r7   = l6 ^ (f(r6, key7));
       // 6. stage
       if (mode[6] == 1'b0) begin
-        c6 = c5(2:27], c5(0:1];
-        d6 = d5(2:27], d5(0:1];
+        c6 = {c5[2:27], c5[0:1]};
+        d6 = {d5[2:27], d5[0:1]};
       end
       else begin
-        c6 = c5(26:27], c5(0:25];
-        d6 = d5(26:27], d5(0:25];
+        c6 = {c5[26:27], c5[0:25]};
+        d6 = {d5[26:27], d5[0:25]};
       end
-      key6 = pc2( ( c6, d6 ) ];
-      l6 = r5;
-      r6 = l5 ^ ( f( r5, key6 ) ];
+      key6 = pc2({c6, d6});
+      l6   = r5;
+      r6   = l5 ^ (f(r5, key6));
       // 5. stage
       if (mode[5] == 1'b0) begin
-        c5 = c4(2:27], c4(0:1];
-        d5 = d4(2:27], d4(0:1];
+        c5 = {c4[2:27], c4[0:1]};
+        d5 = {d4[2:27], d4[0:1]};
       end
       else begin
-        c5 = {c4[26:27], c4(0:25];
-        d5 = {d4[26:27], d4(0:25];
+        c5 = {c4[26:27], c4[0:25]};
+        d5 = {d4[26:27], d4[0:25]};
       end
       key5 = pc2({c5, d5});
       l5   = r4;
       r5   = l4 ^ (f(r4, key5));
       // 4. stage
       if (mode[4] == 1'b0) begin
-        c4 = c3[2:27], c3[0:1]};
-        d4 = d3[2:27], d3[0:1]};
+        c4 = {c3[2:27], c3[0:1]};
+        d4 = {d3[2:27], d3[0:1]};
       end
       else begin
         c4 = {c3[26:27], c3[0:25]};
         d4 = {d3[26:27], d3[0:25]};
       end
-      key4 = pc2({c4, d4}];
+      key4 = pc2({c4, d4});
       l4   = r3;
-      r4   = l3 ^ (f(r3, key4)];
+      r4   = l3 ^ (f(r3, key4));
       // 3. stage
       if (mode[3] == 1'b0) begin
         c3 = {c2[2:27], c2[0:1]};
@@ -401,9 +401,9 @@ module des
         c3 = {c2[26:27], c2[0:25]};
         d3 = {d2[26:27], d2[0:25]};
       end
-      key3 = pc2({c3, d3}];
+      key3 = pc2({c3, d3});
       l3   = r2;
-      r3   = l2 ^ (f(r2, key3)];*/
+      r3   = l2 ^ (f(r2, key3));
       // 2. stage
       if (mode[2] == 1'b0) begin
         c2 = {c1[1:27], c1[0]};