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@ -1,7 +1,9 @@ |
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[](https://github.com/tmeissner/cryptocores/actions?query=workflow%3Atest) |
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# cryptocores |
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# cryptocores |
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cryptography ip-cores in vhdl / verilog |
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Cryptography IP-cores & tests written in VHDL / Verilog |
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The components in this repository are not intended for productional code. |
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The components in this repository are not intended as productional code. |
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They serve as proof of concept, for example how to implement a pipeline using |
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They serve as proof of concept, for example how to implement a pipeline using |
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only (local) variables instead of (global) signals. Furthermore they were used |
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only (local) variables instead of (global) signals. Furthermore they were used |
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how to do a VHDL-to-Verilog conversion for learning purposes. |
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how to do a VHDL-to-Verilog conversion for learning purposes. |
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