move vhdl simulation files into correspondent subdirectory vhdl

aes/sim/makefile

@@ -1,55 +0,0 @@
-# ======================================================================
-# AES encryption/decryption
-# algorithm according to FIPS 197 specification
-# Copyright (C) 2011 Torsten Meissner
-#-----------------------------------------------------------------------
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-# ======================================================================
-
-
-# enable the compile of the OVL library
-# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
-OVL_ENABLE = 1
-
-# the location and sources of the OVL library (copyright of Accellera)
-# OVL is not included in this project, you can download it from
-# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
-OVL_LOC    = ../../../../OVL/
-ifeq ($(OVL_ENABLE), 1)
-  OVL_SRC    = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
-               $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
-               $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
-               $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
-else
-  OVL_SRC =
-endif
-
-all : sim wave
-
-sim : tb_aes.ghw
-
-tb_aes.ghw : ../rtl/*.vhd tb_aes.vhd $(OVL_SRC)
-	ghdl -a --work=accellera_ovl_vhdl $(OVL_SRC)
-	ghdl -a ../rtl/aes_pkg.vhd ../rtl/aes.vhd tb_aes.vhd
-	ghdl -e tb_aes
-	ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us
-	
-wave : tb_aes.ghw
-	gtkwave -T tb_aes.tcl tb_aes.ghw
-	
-clean :
-	echo "# cleaning simulation files"
-	rm -f tb_aes.ghw
-	rm -f *.cf

aes/sim/tb_aes.tcl

@@ -1,10 +0,0 @@
-set signals [list]
-lappend signals "top.tb_aes.s_reset"
-lappend signals "top.tb_aes.s_clk"
-lappend signals "top.tb_aes.s_validin"
-lappend signals "top.tb_aes.s_mode"
-lappend signals "top.tb_aes.s_key"
-lappend signals "top.tb_aes.s_datain"
-lappend signals "top.tb_aes.s_validout"
-lappend signals "top.tb_aes.s_dataout"
-set num_added [ gtkwave::addSignalsFromList $signals ]

aes/sim/tb_aes.vhd

@@ -1,82 +0,0 @@
--- ======================================================================
--- AES encryption/decryption testbench
--- tests according to NIST special publication
--- Copyright (C) 2011 Torsten Meissner
--------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2 of the License, or
--- (at your option) any later version.
-
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
-
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
--- ======================================================================
-
-
--- Revision 0.1   2011/10/22
--- Initial release
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-entity tb_aes is
-end entity tb_aes;
-
-
-architecture rtl of tb_aes is
-
-
-  signal s_reset    : std_logic := '0';
-  signal s_clk      : std_logic := '0';
-  signal s_mode     : std_logic := '0';
-  signal s_key      : std_logic_vector(0 to 127) := (others => '0');
-  signal s_datain   : std_logic_vector(0 to 127) := (others => '0');
-  signal s_validin  : std_logic := '0';
-  signal s_dataout  : std_logic_vector(0 to 127);
-  signal s_validout : std_logic;
-
-
-  component aes is
-    port (
-      reset_i     : in  std_logic;
-      clk_i       : in  std_logic;
-      mode_i      : in  std_logic;
-      key_i       : in  std_logic_vector(0 TO 127);
-      data_i      : in  std_logic_vector(0 TO 127);
-      valid_i     : in  std_logic;
-      data_o      : out std_logic_vector(0 TO 127);
-      valid_o     : out std_logic
-    );
-  end component aes;
-
-
-begin
-
-
-  s_clk   <= not(s_clk) after 10 ns;
-  s_reset <= '1' after 100 ns;
-
-
-  i_aes : aes
-  port map (
-    reset_i  => s_reset,
-    clk_i    => s_clk,
-    mode_i   => s_mode,
-    key_i    => s_key,
-    data_i   => s_datain,
-    valid_i  => s_validin,               
-    data_o   => s_dataout,
-    valid_o  => s_validout
-  );
-
-
-end architecture rtl;