you can now include the OVL library if you set the OVL_ENABLE flag to 1

- new variable OVL_ENABLE to enable OVL compile
- new variables OVL_LOC & OVL_SRC which point to the OVL library files
- new GHDL analyze of the OVL library

aes/sim/makefile

@@ -19,15 +19,29 @@
 # ======================================================================
 
 
-# Revision 0.1  2011/10/22
-# Initial release
-
+# enable the compile of the OVL library
+# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
+OVL_ENABLE = 0
+
+# the location and sources of the OVL library (copyright of Accellera)
+# OVL is not included in this project, you can download it from
+# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
+OVL_LOC    = ../../../../OVL/
+ifeq ($(OVL_ENABLE), 1)
+  OVL_SRC    = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
+               $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
+               $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
+               $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
+else
+  OVL_SRC =
+endif
 
 all : sim wave
 
 sim : tb_aes.ghw
 
-tb_aes.ghw : ../rtl/*.vhd tb_aes.vhd
+tb_aes.ghw : ../rtl/*.vhd tb_aes.vhd $(OVL_SRC)
+	ghdl -a $(OVL_SRC)
 	ghdl -a ../rtl/aes_pkg.vhd ../rtl/aes.vhd tb_aes.vhd
 	ghdl -e tb_aes
 	ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us

cbcdes/sim/makefile

@@ -19,15 +19,29 @@
 # ======================================================================
 
 
-# Revision 1.0  2011/09/23
-# Initial release
-
+# enable the compile of the OVL library
+# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
+OVL_ENABLE = 0
+
+# the location and sources of the OVL library (copyright of Accellera)
+# OVL is not included in this project, you can download it from
+# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
+OVL_LOC    = ../../../../OVL/
+ifeq ($(OVL_ENABLE), 1)
+  OVL_SRC    = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
+               $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
+               $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
+               $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
+else
+  OVL_SRC =
+endif
 
 all : sim wave
 
 sim : tb_cbcdes.ghw
 
-tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd
+tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd $(OVL_SRC)
+	ghdl -a $(OVL_SRC)
 	ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/cbcdes.vhd tb_cbcdes.vhd
 	ghdl -e tb_cbcdes
 	ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=220us

cbctdes/sim/makefile

@@ -19,11 +19,30 @@
 # ======================================================================
 
 
+# enable the compile of the OVL library
+# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
+OVL_ENABLE = 0
+
+# the location and sources of the OVL library (copyright of Accellera)
+# OVL is not included in this project, you can download it from
+# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
+OVL_LOC    = ../../../../OVL/
+ifeq ($(OVL_ENABLE), 1)
+  OVL_SRC    = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
+               $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
+               $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
+               $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
+else
+  OVL_SRC =
+endif
+
+
 all : sim wave
 
 sim : tb_cbctdes.ghw
 
-tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd
+tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd $(OVL_SRC)
+	ghdl -a $(OVL_SRC)
 	ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd ../rtl/cbctdes.vhd tb_cbctdes.vhd
 	ghdl -e tb_cbctdes
 	ghdl -r tb_cbctdes --wave=tb_cbctdes.ghw --assert-level=error --stop-time=45us

tdes/sim/makefile

@@ -19,15 +19,30 @@
 # ======================================================================
 
 
-# Revision 1.0  2011/09/23
-# Initial release
+# enable the compile of the OVL library
+# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
+OVL_ENABLE = 0
+
+# the location and sources of the OVL library (copyright of Accellera)
+# OVL is not included in this project, you can download it from
+# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
+OVL_LOC    = ../../../../OVL/
+ifeq ($(OVL_ENABLE), 1)
+  OVL_SRC    = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
+               $(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
+               $(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
+               $(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
+else
+  OVL_SRC =
+endif
 
 
 all : sim wave
 
 sim : tb_tdes.ghw
 
-tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd
+tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd $(OVL_SRC)
+	ghdl -a $(OVL_SRC)
 	ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd
 	ghdl -e tb_tdes
 	ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us