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new stimuli, checker & reset processes

master
Torsten Meissner 12 years ago
parent
commit
9a29954670
1 changed files with 51 additions and 16 deletions
  1. +51
    -16
      des/sim/verilog/tb_des.v

+ 51
- 16
des/sim/verilog/tb_des.v View File

@ -27,39 +27,74 @@ module tb_des;
$dumpvars (0, tb_des);
end
reg reset;
reg clk = 0;
reg mode;
reg [0:63] key;
reg [0:63] datain;
reg validin;
integer index;
integer outdex;
wire [0:63] dataout;
wire validout;
reg [0:63] variable_plaintext_known_answers [0:63];
reg reset = 0;
initial begin
$readmemh("stimuli.txt", variable_plaintext_known_answers);
end
initial begin
reset = 1;
#1 reset = 0;
#20 reset = 1;
#1000 $finish;
end
reg clk = 0;
always #5 clk = !clk;
reg mode;
reg [0:63] key;
reg [0:63] datain;
reg validin;
always @(posedge clk, reset) begin
if(~reset) begin
initial
forever @(negedge reset) begin
disable stimuli;
disable checker;
mode <= 0;
validin <= 0;
key <= 0;
datain <= 0;
end
else begin
mode <= 1;
always begin : stimuli
wait (reset)
@(posedge clk)
// Variable plaintext known answer test
datain <= 64'h8000000000000000;
mode <= 0;
validin <= 1;
key <= key + 1;
datain <= datain + 1;
end
key <= 64'h0101010101010101;
for(index = 0; index < 64; index = index + 1)
begin
@(posedge clk)
datain <= {1'b0, datain[0:62]};
end
validin <= 0;
end
wire [0:63] dataout;
wire validout;
always begin : checker
wait (reset)
// Variable plaintext known answer test
wait (validout)
for(outdex = 0; outdex < 64; outdex = outdex + 1)
begin
@(posedge clk)
if (dataout == variable_plaintext_known_answers[outdex]) begin
$display ("okay");
end else begin
$display ("error, output was %h - should have been %h", dataout, variable_plaintext_known_answers[outdex]);
end
end
@(posedge clk)
$finish;
end
des i_des (
.reset_i(reset),


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