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@ -82,8 +82,12 @@ package aes_pkg is |
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function shiftrow (input : t_datatable2d) return t_datatable2d; |
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function shiftrow (input : t_datatable2d) return t_datatable2d; |
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-- function mixcolumns (input : t_datatable2d) return t_datatable2d; |
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function sortdata (input : std_logic_vector(127 downto 0)) return t_datatable2d; |
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function sortdata (input : std_logic_vector(127 downto 0)) return t_datatable2d; |
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function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector; |
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end package aes_pkg; |
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end package aes_pkg; |
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@ -134,4 +138,26 @@ package body aes_pkg is |
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end function shiftrow; |
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end function shiftrow; |
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function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector is |
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variable v_a, v_b : std_logic_vector(7 downto 0); |
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variable v_data : std_logic_vector(7 downto 0) := (others => '0'); |
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variable v_hi_bit_set : std_logic := '0'; |
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begin |
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v_a := a; |
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v_b := b; |
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for index in 0 to 7 loop |
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if(b(0) = '1') then |
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v_data := v_data xor a; |
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end if; |
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v_hi_bit_set := a(7); |
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v_a := v_a(6 downto 0) & '0'; |
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if(v_hi_bit_set = '1') then |
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v_a := v_a xor x"01"; |
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end if; |
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v_b := '0' & v_b(7 downto 1); |
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end loop; |
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return v_data; |
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end function gmul; |
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end package body aes_pkg; |
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end package body aes_pkg; |