Implement key schedule for AES decryption, unoptimized

aes/rtl/vhdl/aes_dec.vhd

@@ -48,24 +48,6 @@ end entity aes_dec;
 architecture rtl of aes_dec is
 
 
-  -- Fixed round keys for verification until key schedule is implemented
-  type t_key_array is array (11 downto 1) of t_key;
-  constant c_round_keys : t_key_array := (
-    (x"2b7e1516", x"28aed2a6", x"abf71588", x"09cf4f3c"),
-    (x"a0fafe17", x"88542cb1", x"23a33939", x"2a6c7605"),
-    (x"f2c295f2", x"7a96b943", x"5935807a", x"7359f67f"),
-    (x"3d80477d", x"4716fe3e", x"1e237e44", x"6d7a883b"),
-    (x"ef44a541", x"a8525b7f", x"b671253b", x"db0bad00"),
-    (x"d4d1c6f8", x"7c839d87", x"caf2b8bc", x"11f915bc"),
-    (x"6d88a37a", x"110b3efd", x"dbf98641", x"ca0093fd"),
-    (x"4e54f70e", x"5f5fc9f3", x"84a64fb2", x"4ea6dc4f"),
-    (x"ead27321", x"b58dbad2", x"312bf560", x"7f8d292f"),
-    (x"ac7766f3", x"19fadc21", x"28d12941", x"575c006e"),
-    (x"d014f9a8", x"c9ee2589", x"e13f0cc8", x"b6630ca6")
-  );
-  signal s_round_key : t_key := (others => (others => '0'));
-
-
 begin
 
 
@@ -78,11 +60,10 @@ begin
   begin
 
 
-    s_round_key <= c_round_keys(s_round) when s_round >= 1 and s_round <= 11 else
-                   (others => (others => '0'));
-
     DeCryptP : process (reset_i, clk_i) is
-      variable v_state : t_datatable2d;
+      variable v_state      : t_datatable2d;
+      type t_key_array is array (0 to 10) of t_key;
+      variable v_round_keys : t_key_array;
     begin
       if (reset_i = '0') then
         v_state  := (others => (others => (others => '0')));
@@ -98,17 +79,21 @@ begin
             if (accept_o = '1' and valid_i = '1') then
               accept_o <= '0';
               v_state  := set_state(data_i);
+              v_round_keys(0) := set_key(key_i);
+              for i in t_key_rounds'low to t_key_rounds'high loop
+                v_round_keys(i+1) := key_round(v_round_keys(i), i);
+              end loop;
               s_round  <= s_round + 1;
             end if;
 
           when 1 =>
-            v_state := addroundkey(v_state, s_round_key);
+            v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
             s_round <= s_round + 1;
 
           when t_dec_rounds'high-1 =>
             v_state := invshiftrow(v_state);
             v_state := invsubbytes(v_state);
-            v_state := addroundkey(v_state, s_round_key);
+            v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
             s_round <= s_round + 1;
             -- set data & valid to save one cycle
             valid_o <= '1';
@@ -126,7 +111,7 @@ begin
           when others =>
             v_state := invshiftrow(v_state);
             v_state := invsubbytes(v_state);
-            v_state := addroundkey(v_state, s_round_key);
+            v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
             v_state := invmixcolumns(v_state);
             s_round <= s_round + 1;
 

aes/rtl/vhdl/aes_pkg.vhd

@@ -76,7 +76,7 @@ package aes_pkg is
   constant c_nr : natural := 10;  -- number of rounds
 
   subtype t_rounds is natural range 0 to c_nr + 1;
-  subtype t_key_rounds is natural range c_nk to c_nb * (c_nr + 1);
+  subtype t_key_rounds is natural range 0 to 9;
   subtype t_enc_rounds is natural range t_rounds'low to t_rounds'high+1;
   subtype t_dec_rounds is natural range t_rounds'low to t_rounds'high+1;
 
@@ -151,7 +151,7 @@ package aes_pkg is
 
   function rotword (input : in std_logic_vector(31 downto 0)) return std_logic_vector;
 
-  function key_round (key : t_key; round : t_enc_rounds) return t_key;
+  function key_round (key : t_key; round : t_key_rounds) return t_key;
 
   function set_state (input : in std_logic_vector(0 to 127)) return t_datatable2d;
 
@@ -337,7 +337,7 @@ package body aes_pkg is
   end function rotword;
 
 
-  function key_round (key : t_key; round : t_enc_rounds) return t_key is
+  function key_round (key : t_key; round : t_key_rounds) return t_key is
     variable v_key : t_key;
   begin
     v_key(3) := subword(rotword(key(3))) xor (c_rcon(round) & x"000000");

aes/sim/vhdl/tb_aes.vhd

@@ -77,6 +77,7 @@ architecture rtl of tb_aes is
     return v_data;
   end function;
 
+
 begin
 
 
@@ -145,7 +146,7 @@ begin
     for i in 0 to 63 loop
       wait until rising_edge(s_clk);
       s_validin_dec <= '1';
-      v_key         := x"2b7e151628aed2a6abf7158809cf4f3c";
+      v_key         := v_random.RandSlv(128);
       v_datain      := v_random.RandSlv(128);
       s_key         <= v_key;
       s_datain      <= v_datain;