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minor updates

master
Torsten Meissner 13 years ago
parent
commit
d3314a7d46
2 changed files with 2 additions and 2 deletions
  1. +1
    -1
      tdes/sim/makefile
  2. +1
    -1
      tdes/sim/tb_tdes.vhd

+ 1
- 1
tdes/sim/makefile View File

@ -30,7 +30,7 @@ sim : tb_tdes.ghw
tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd
ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd
ghdl -e tb_tdes ghdl -e tb_tdes
ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=100us
ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us
wave : tb_tdes.ghw wave : tb_tdes.ghw
gtkwave tb_tdes.ghw gtkwave tb_tdes.ghw


+ 1
- 1
tdes/sim/tb_tdes.vhd View File

@ -58,7 +58,7 @@ architecture rtl of tb_tdes is
signal s_validin : std_logic := '0'; signal s_validin : std_logic := '0';
signal s_ready : std_logic := '0'; signal s_ready : std_logic := '0';
signal s_dataout : std_logic_vector(0 to 63); signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic;
signal s_validout : std_logic := '0';
component tdes is component tdes is


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