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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
200
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
1850e5c1e3
cryptocores
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.gitmodules
3 lines
84 B
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[submodule "lib/osvvm"]
path = lib/osvvm
url = https://github.com/OSVVM/OSVVM.git