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162 lines
4.1 KiB
162 lines
4.1 KiB
// ======================================================================
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// CBC-DES encryption/decryption
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// algorithm according to FIPS 46-3 specification
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// Copyright (C) 2013 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write:the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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`timescale 1ns/1ps
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module cbctdes
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(
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input reset_i, // async reset
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input clk_i, // clock
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input start_i, // start cbc
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input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
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input [0:63] key1_i, // key input
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input [0:63] key2_i, // key input
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input [0:63] key3_i, // key input
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input [0:63] iv_i, // iv input
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input [0:63] data_i, // data input
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input valid_i, // input key/data valid flag
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output reg ready_o, // ready to encrypt/decrypt
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output reg [0:63] data_o, // data output
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output valid_o // output data valid flag
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);
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reg mode;
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wire tdes_mode;
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reg start;
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reg [0:63] key;
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wire [0:63] tdes_key1;
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wire [0:63] tdes_key2;
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wire [0:63] tdes_key3;
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reg [0:63] key1;
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reg [0:63] key2;
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reg [0:63] key3;
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reg [0:63] iv;
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reg [0:63] datain;
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reg [0:63] datain_d;
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reg [0:63] tdes_datain;
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wire validin;
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wire [0:63] tdes_dataout;
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reg reset;
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reg [0:63] dataout;
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wire tdes_ready;
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always @(*) begin
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if (~mode_i && start_i) begin
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tdes_datain = iv_i ^ data_i;
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end
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else if (~mode && ~start_i) begin
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tdes_datain = dataout ^ data_i;
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end
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else begin
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tdes_datain = data_i;
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end
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end
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always @(*) begin
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if (mode && start) begin
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data_o = iv ^ tdes_dataout;
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end
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else if (mode && ~start) begin
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data_o = datain_d ^ tdes_dataout;
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end
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else begin
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data_o = tdes_dataout;
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end
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end
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assign tdes_key1 = start_i ? key1_i : key1;
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assign tdes_key2 = start_i ? key2_i : key2;
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assign tdes_key3 = start_i ? key3_i : key3;
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assign validin = valid_i & ready_o;
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// input register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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reset <= 0;
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mode <= 0;
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start <= 0;
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key1 <= 0;
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key2 <= 0;
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key3 <= 0;
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iv <= 0;
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datain <= 0;
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datain_d <= 0;
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end
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else begin
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reset <= reset_i;
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if (valid_i && ready_o) begin
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start <= start_i;
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datain <= data_i;
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datain_d <= datain;
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end
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else if (valid_i && ready_o && start_i) begin
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mode <= mode_i;
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key1 <= key1_i;
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key2 <= key2_i;
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key3 <= key3_i;
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iv <= iv_i;
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end
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end
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end
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// output register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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ready_o <= 0;
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dataout <= 0;
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end
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else begin
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if (valid_i && ready_o && tdes_ready) begin
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ready_o <= 0;
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end
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else if (valid_o || (reset_i && ~reset)) begin
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ready_o <= 1;
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dataout <= tdes_dataout;
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end
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end
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end
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// des instance
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tdes i_tdes (
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.reset_i(reset),
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.clk_i(clk_i),
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.mode_i(tdes_mode),
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.key1_i(tdes_key1),
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.key2_i(tdes_key2),
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.key3_i(tdes_key3),
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.data_i(tdes_datain),
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.valid_i(validin),
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.data_o(tdes_dataout),
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.valid_o(valid_o),
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.ready_o(tdes_ready)
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);
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endmodule
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