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125 lines
3.3 KiB
125 lines
3.3 KiB
-- ======================================================================
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-- AES Counter mode testbench
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-- Copyright (C) 2020 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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use std.env.all;
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entity tb_ctraes is
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end entity tb_ctraes;
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architecture sim of tb_ctraes is
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constant C_NONCE_WIDTH : natural range 64 to 96 := 96;
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signal s_reset : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_start : std_logic := '0';
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signal s_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1) := (others => '0');
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signal s_key : std_logic_vector(0 to 127) := (others => '0');
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signal s_datain : std_logic_vector(0 to 127) := (others => '0');
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signal s_validin : std_logic := '0';
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signal s_acceptin : std_logic;
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signal s_dataout : std_logic_vector(0 to 127);
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signal s_validout : std_logic := '0';
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signal s_acceptout : std_logic := '0';
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begin
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i_ctraes : entity work.ctraes
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generic map (
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NONCE_WIDTH => C_NONCE_WIDTH
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)
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port map (
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reset_i => s_reset,
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clk_i => s_clk,
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start_i => s_start,
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nonce_i => s_nonce,
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key_i => s_key,
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data_i => s_datain,
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valid_i => s_validin,
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accept_o => s_acceptin,
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data_o => s_dataout,
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valid_o => s_validout,
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accept_i => s_acceptout
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);
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s_clk <= not(s_clk) after 10 ns;
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s_reset <= '1' after 100 ns;
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process is
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variable v_random : RandomPType;
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begin
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v_random.InitSeed(v_random'instance_name);
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wait until s_reset = '1' and rising_edge(s_clk);
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-- ENCRYPTION TESTs
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report "Test encryption";
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for i in 0 to 31 loop
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if (i = 0) then
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s_start <= '1';
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s_nonce <= v_random.RandSlv(s_nonce'length);
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else
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s_start <= '0';
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end if;
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s_validin <= '1';
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s_key <= v_random.RandSlv(128);
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s_datain <= v_random.RandSlv(128);
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report "Test #" & to_string(i);
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wait until s_acceptin = '1' and rising_edge(s_clk);
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s_validin <= '0';
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end loop;
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-- Watchdog
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wait for 1 us;
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report "Watchdog error"
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severity failure;
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end process;
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process is
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begin
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s_acceptout <= '0';
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for i in 0 to 31 loop
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wait until s_validout = '1' and rising_edge(s_clk);
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s_acceptout <= '1';
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wait until rising_edge(s_clk);
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s_acceptout <= '0';
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end loop;
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report "Tests finished";
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wait for 100 ns;
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finish(0);
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end process;
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end architecture sim;
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