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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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216
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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250fbf34b3
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cryptocores
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lib
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T. Meissner
d16c247b5c
Add OSVVM as submodule
4 years ago
..
osvvm
@
d9a1518e3d
Add OSVVM as submodule
4 years ago