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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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187
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
28b2cd3856
master
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cryptocores
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cbcdes
/
sim
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vhdl
History
T. Meissner
51745c47d3
adapt to new directory structure
12 years ago
..
makefile
adapt to new directory structure
12 years ago
tb_cbcdes.tcl
moved in seperate directory 'vhdl'
12 years ago
tb_cbcdes.vhd
moved in seperate directory 'vhdl'
12 years ago