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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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VHDL
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Verilog
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Makefile
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Tcl
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[submodule "lib/osvvm"]
path = lib/osvvm
url = https://github.com/OSVVM/OSVVM.git