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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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175
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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313a08b6f3
master
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cryptocores
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tdes
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rtl
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verilog
History
T. Meissner
fa93856e07
removed internal synced copy of reset; set ready to high in reset
10 years ago
..
des.v
import of des verilog design files
12 years ago
des_pkg.v
import of des verilog design files
12 years ago
tdes.v
removed internal synced copy of reset; set ready to high in reset
10 years ago